MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 870

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.11 Hardware Assist for IEEE1588 Compliant Timestamping
IEEE 1588 compliant timestamping on this device is accomplished using the per-port transmit
timestamping registers within each Ethernet controller memory space (See
Time Stamp Identification Register
Stamp Register
located within the memory space for eTSEC1. Because the common 1588 timestamping registers exist
within the eTSEC1 memory space, the eTSEC1 controller must remain enabled in order to use 1588
timestamping for any Ethernet port.
14.5.3.11.1 Timer Control Register (TMR_CTRL)
This register is used to reset, configure, and initialize the eTSEC precision timer clock. The control of all
timer function is performed via programming eTSEC1.The register in eTSEC1 is shared for all eTSECs.
Figure 14-7 describes the definition for the TMR_CTRL register.
Register fields not described below are reserved.
Table 14-114
reserved.
14-122
Offset eTSEC1:0x2_4E00
Reset
Reset
Bits
0
1
3
4
W
W
R
R
ALM1P ALM2P
RTPE
16
0
0
0
ALM1P
ALM2P
Name
PP1L
FS
describes the fields of the TMR_CTRL register. Register fields not described below are
FRD
(TMR_TXTS1–2_H/L).”) in conjunction with the following common registers, which are
17
1
0
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Alarm1 output polarity
0 active high output
1 active low output
Alarm2 output polarity
0 active high output
1 active low output
FIPER start indication
0 Fiper is enabled through timer enable
1 Fiper is enabled through timer enable and alarm indication.
Fiper1 pulse loopback mode enabled.
0 Trigger1 input is based upon normal external trigger input.
1 Fiper1 pulse is looped back into Trigger1 input.
—
18
—
0
0
2
Table 14-114. TMR_CTRL Register Field Descriptions
FS
—
19
0
0
3
Figure 14-110. TMR_CTRL Register Definition
ESFDP ESFDE ETEP2 ETEP1 COPH CIPH TMSR
PP1L
20
0
0
4
(TMR_TXTS1–2_ID),” and
PP2L
21
5
0
0
22
0
0
6
23
Description
0
0
24
Section 14.5.3.2.13, “Transmit Time
0
0
TCLK_PERIOD
25
0
0
Section 14.5.3.2.12, “Transmit
26
0
0
27
—
0
0
Freescale Semiconductor
BYP
28
0
0
Access: Mixed
TE
29
0
0
CKSEL
30
0
0
15
31
1
1