MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 340

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
If a transaction request is issued to the DDR memory controller and the address does not lie within any of
the programmed address ranges for an enabled chip select, a memory select error is flagged. Errors are
described in detail in
Using a memory-polling algorithm at power-on reset or by querying the JEDEC serial presence detect
capability of memory modules, system firmware uses the memory-boundary registers to configure the
DDR memory controller to map the size of each bank in memory. The memory controller uses its bank
map to assert the appropriate MCSn signal for memory accesses according to the provided bank starting
and ending addresses. The memory banks are not required to be mapped to a contiguous address space.
8.5.2
The following tables (,
configuration. The address presented at the memory controller signals MA[15:0] use MA[15] as the msb
and MA[0] as the lsb. Also, MA[10] is used as the auto-precharge bit in DDR2/DDR3 modes for reads and
writes, so the column address can never use MA[10].
8-66
SDRAM Device
512 Mbits
512 Mbits
DDR SDRAM Address Multiplexing
Table 8-54. Supported DDR2 SDRAM Device Configurations—One Physical Bank
1 Gbits
1 Gbits
2 Gbits
2 Gbits
4 Gbits
4 Gbits
SDRAM Device
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
256 Mbits
256 Mbits
512 Mbits
512 Mbits
1 Gbits
1 Gbits
2 Gbits
2 Gbits
Section 8.5.12, “Error Management.”
Table 8-53. Supported DDR3 SDRAM Device Configurations
Table
Device Configuration
128Mbits x 16
256Mbits x 16
32 Mbits x 16
128 Mbits x 8
64 Mbits x 16
256Mbits x 8
512Mbits x 8
64 Mbits x 8
8-55,
Device Configuration
Table
128Mbits x 16
16 Mbits x 16
32 Mbits x 16
128 Mbits x 8
64 Mbits x 16
256Mbits x 8
32 Mbits x 8
64 Mbits x 8
8-56) show the address bit encodings for each DDR SDRAM
Row x Column x
Sub-bank Bits
13 x 10 x 3
12 x 10 x 2
14 x 10 x 3
13 x 10 x 3
15 x 10 x 3
14 x 10 x 3
16 x 10 x 3
15 x 10 x 3
Row x Column x
Sub-bank Bits
13 x 10 x 2
14 x 10 x 2
13 x 10 x 2
14 x 10 x 3
13 x 10 x 3
14 x 11 x 3
14 x 10 x 3
13 x 9 x 2
64-Bit Bank Size
512 Mbytes
256 Mbytes
512 Mbytes
2 Gbytes
4 Gbytes
2 Gbytes
1 Gbyte
1 Gbyte
16-Bit Bank Size
128 Mbytes
256 Mbytes
128 Mbytes
512 Mbytes
256 Mbytes
64 Mbytes
32 Mbytes
64 Mbytes
Four Banks of
Freescale Semiconductor
16 Gbytes
2 Gbytes
4 Gbytes
2 Gbytes
8 Gbytes
4 Gbytes
8 Gbytes
Memory
1 Gbyte