MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 628

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DUART
12.3.1.6
The UFCR, a write-only register, is used to enable and clear the receiver and transmitter FIFOs, set a
receiver FIFO trigger level to control the received data available interrupt, and select the type of DMA
signaling.
When the UFCR bits are written, the FIFO enable bit must also be set or else the UFCR bits are not
programmed. When changing from FIFO mode to 16450 mode (non-FIFO mode) and vice versa, data is
automatically cleared from the FIFOs.
After all the bytes in the receiver FIFO are cleared, the receiver internal shift register is not cleared.
Similarly, the bytes are cleared in the transmitter FIFO, but the transmitter internal shift register is not
cleared. Both TFR and RFR are self-clearing bits.
Figure 12-8
Table 12-11
12-10
IID[3–0]
IID Bits
0b0010
0b0000
Bits
0–1
2–3
4
Offset UART0: 0x502, UART1: 0x602
Reset
Name
DMS
RTL
W
Priority
—
R
Fourth
Level
Third
shows the bits in the UFCRs.
describes the fields of the UFCRs.
Receiver trigger level. A received data available interrupt occurs when UIER[ERDAI] is set and the number of
bytes in the receiver FIFO equals the designated interrupt trigger level as follows:
00 1 byte
01 4 bytes
10 8 bytes
11 14 bytes
Reserved
DMA mode select. See
0 UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 0.
1 UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 1 if UFCR[FEN] = 1.
FIFO Control Registers (UFCR n ) (ULCR[DLAB] = 0)
0
UTHR empty
Modem status
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Interrupt Type
RTL
Table 12-10. UIIR IID Bits Summary (continued)
1
Figure 12-8. FIFO Control Registers (UFCR n )
Table 12-11. UFCR Field Descriptions
Section 12.4.5.2, “DMA Mode Select,”
Transmitter holding register is empty
CTS input value changed since last read of
UMSR
2
—
Interrupt Description
3
All zeros
Description
DMS
4
for more information.
TFR
5
Read the UIIR or write to the
UTHR.
Read the UMSR.
How To Reset Interrupt
Freescale Semiconductor
RFR
6
Access: Write only
FEN
7