MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 195

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

operation is asynchronous with respect to SYSCLK and the platform clock. If the separate (asynchronous)
PCI_CLK clock signal is used rather than SYSCLK as the PCI clock, then this clock must be constantly
driven, even when in Deep Sleep mode, in order to avoid loss of lock.
The DDR memory controller complex may use the platform clock and thus have operation of the DDR
interface be synchronous with the platform. Alternately, an independent clock, DDRCLK, may be multiplied
up using a separate PLL to create a unique DDR memory controller complex clock. In this case, the DDR
complex operates asynchronously with respect to the platform clock.
4.4.4.2
Clocks for these high speed interfaces on the MPC8536E are derived from a PLL in the SerDes block. This
PLL is driven by a reference clock (SDn_REF_CLK/SDn_REF_CLK) whose input frequency is a function
of the protocol and bit rate being used as shown in
Freescale Semiconductor
cfg_core_pll[0:2]
cfg_sys_pll[0:3]
PCI_CLK
cfg_ddr_pll[0:2]
SYSCLK
DDRCLK
PCI Express and SGMII Clocks
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PCI Express
Interfaces
MPC8536E
SGMII
4
3
3
Device PLL
Figure 4-6. Clock Subsystem Block Diagram
Complex
Table 4-34. High Speed Interface Clocking
e500 Core
DDR
PLL
x
PCI
1.25 Gbps
2.5 Gbps
Bit Rate
CCB_clk
Core PLL
CCB_clk to rest
of the device
Table
100 MHz (Spread Spectrum supported)
n
4-34.
2 or 4
Reference Clock Frequency
core_clk
PLL
100 MHz
DDR
6
6
Reset, Clocking, and Initialization
LSYNC_IN
LSYNC_OUT
LCLK0
LCLK1
LCLK2
MCK[0:5]
MCK[0:5]
DDR
Controller
LBC
4-25