MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1221

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 18-4
Table 18-5
18.3.1.3
The eSPI mask register (SPIM) enables/masks interrupts for events recognized by the eSPI. When an event
is recognized, the eSPI sets the corresponding SPIE bit. Setting a bit in the eSPI mask register (SPIM)
Freescale Semiconductor
Offset 0x004
Reset
Reset
W
W
10–15 TXCNT The current number of free Tx FIFO bytes
24–31
R
R
Bits
0–1
2–7
8–9
16
17
18
19
20
21
22
23
TXE
16
0
0
RXCNT The current number of full Rx FIFO bytes
—
Name
describes the SPIE fields.
DON
RNE
TXE
RXT
RXF
TXT
TNF
shows the eSPI event register.
—
—
—
—
DON
eSPI Mask Register (SPIM)
17
1
0
Note—For character lengths of 9 to 16 bits—each character occupies 2 bytes in Rx/Tx FIFO
Note—For character lengths of 9 to 16 bits—each character occupies 2 bytes in Rx/Tx FIFO
Tx FIFO is empty
Last character was transmitted .
The last character was transmitted and a new command can be written for the next frame
Rx FIFO has more than RXTHR bytes i.e. at least RXTHR+1 bytes
Rx FIFO is full
Tx FIFO has less than TXTHR bytes.i.e. at most TXTHR–1 bytes
Not empty. Indicates that the Rx FIFO register contains a received character.
0 The Rx FIFO is empty
1 The Rx FIFO has a received character. The core can read the content of Rx FIFO through SPIRF.
Tx FIFO not full.
0 The transmitter FIFO is full.
1 The transmitter FIFO is not full.
Reserved, should be cleared.
Reserved, should be cleared.
Reserved, should be cleared.
Reserved, should be cleared.
RXT
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
18
0
2
RXF
19
0
TXT
20
Figure 18-4. eSPI Event Register (SPIE)
0
RXCNT
Table 18-5. SPIE Field Descriptions
—
21
0
RNE
22
0
TNF
23
0
7
All zeros
Description
24
0
8
—
0
9
10
1
Enhanced Serial Peripheral Interface
0
—
0
TXCNT
0
Access: Mixed
0
15
31
18-7
0