MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1456

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.8
The function of the device operation is to transfer a request in the memory image to and from the Universal
Serial Bus. Using a set of linked list transfer descriptors, pointed to by a queue head, the device controller
will perform the data transfers. The following sections explain the use of the device controller from the
device controller driver (DCD) point-of-view and further describe how specific USB bus events relate to
status changes in the device controller programmer's interface.
21.8.1
After hardware reset, the USB DR module is disabled until the run/stop bit (USBCMD[RS]) is set to a '1'.
In the disabled state, the pull-up on the USB D+ is not active which prevents an attach event from
occurring. At a minimum, it is necessary to have the queue heads setup for endpoint zero before the device
attach occurs. Shortly after the device is enabled, a USB reset will occur followed by setup packet arriving
at endpoint 0. A queue head must be prepared so that the device controller can store the incoming setup
packet.
In order to initialize a device, the software should perform the following steps:
21-122
31–12 Buffer Pointer. Selects the page offset in memory for the packet buffer. Non virtual memory systems will typically set
31–12 Buffer Pointer. Selects the page offset in memory for the packet buffer. Non virtual memory systems will typically set
10–0
11–0
Bits
Bits
11
1. Set the controller mode to device mode. Optionally set USBMODE[SDIS] (streaming disable).
2. Optionally modify the BURSTSIZE register.
3. Program PORTSC[PTS] if using a non-ULPI PHY.
4. Set CONTROL[USB_EN]
5. Allocate and initialize device queue heads in system memory Minimum: Initialize device queue
heads 0 Tx and 0 Rx.
the buffer pointers to a series of incrementing integers.
Reserved
Frame Number. Written by the device controller to indicate the frame number in which a packet finishes. This is typically
be used to correlate relative completion times of packets on an ISO endpoint.
the buffer pointers to a series of incrementing integers.
Reserved
Device Operational Model
Device Controller Initialization
Transitioning from host mode to device mode requires a device controller
reset before modifying USBMODE.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-81. Buffer Pointer Pages 2–4
Table 21-80. Buffer Pointer Page 1
NOTE
Description
Description
Freescale Semiconductor