MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1385

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.5.4.5
DWord 6 of a siTD is simply another schedule link pointer. This pointer is always zero, or references a
siTD. This pointer cannot reference any other schedule data structure.
21.5.5
This data structure is only used with a queue head. This data structure is used for one or more USB
transactions. This data structure is used to transfer up to 20480 (5
two structure pointers used for queue advancement, a DWord of transfer state, and a five-element array of
data buffer pointers. This structure is 32 bytes (or one 32-byte cache line). This data structure must be
physically contiguous.
The buffer associated with this transfer must be virtually contiguous. The buffer may start on any byte
boundary. A separate buffer pointer list element must be used for each physical page in the buffer,
regardless of whether the buffer is physically contiguous.
Host controller updates (host controller writes) to stand-alone qTDs only occur during transfer retirement.
References in the following bit field definitions of updates to the qTD are to the qTD portion of a queue
head.
Freescale Semiconductor
31–12
11–5
31–5
Bits
Bits
4–3
2–0
4–1
0
Buffer Pointer
Back Pointer
(Page 1)
T-Count
Queue Element Transfer Descriptor (qTD)
Name
Name
siTD Back Link Pointer
TP
—
—
T
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Bits 31–12 are 4K page-aligned, physical memory addresses. These bits correspond to physical
address bits 31–12 respectively. The field P specifies the current active pointer
Reserved, should be cleared.
Transaction position. This field is used with T-count to determine whether to send all, first, middle,
or last with each outbound transaction payload. System software must initialize this field with the
appropriate starting value. The host controller must correctly manage this state during the lifetime
of the transfer. The bit encodings are:
00 All. The entire full-speed transaction data payload is in this transaction (that is, less than or equal
01 Begin. This is the first data payload for a full-speed transaction that is greater than 188 bytes.
10 Mid. This is the middle payload for a full-speed OUT transaction that is larger than 188 bytes.
11 End. This is the last payload for a full-speed OUT transaction that was larger than 188 bytes.
Transaction count. Software initializes this field with the number of OUT start-splits this transfer
requires. Any value larger than 6 is undefined.
A physical memory pointer to an siTD
Reserved, should be cleared. This field is reserved for future use. It should be cleared.
Terminate
0 siTD Back Pointer field is valid
1 siTD Back Pointer field is not valid
to 188 bytes).
Table 21-49. siTD Buffer Pointer Page 1 (Plus)
Table 21-50. siTD Back Link Pointer
Description
Description
4096) bytes. The structure contains
Universal Serial Bus Interfaces
21-51