MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 639

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The baud rate is defined as the number of bits per second that can be sent over the UART bus. The formula
for calculating baud rate is as follows:
Therefore, the output frequency of the baud-rate generator is 16 times the baud rate.
The divisor value is determined by the following two 8-bit registers to form a 16-bit binary number:
Upon loading either of the divisor latches, a 16-bit baud-rate counter is loaded.
The divisor latches must be loaded during initialization to ensure proper operation of the baud-rate
generator. Both UART devices on the same bus must be programmed for the same baud-rate before starting
a transfer.
The baud clock can be passed to the performance monitor by enabling the UAFR[BO] bit. This can be used
to determine baud rate errors.
12.4.3
Local loopback mode is provided for diagnostic testing. The data written to UTHR can be read from the
receiver buffer register (URBR) of the same UART. In this mode, the modem control register UMCR[RTS]
is internally tied to the modem status register UMSR[CTS]. The transmitter SOUT is set to a logic 1 and
the receiver SIN is disconnected. The output of the transmitter shift register is looped back into the receiver
shift register input. The CTS (input signal) is disconnected, RTS is internally connected to CTS, and the
RTS (output signal) becomes inactive. In this diagnostic mode, data that is transmitted is immediately
received. In local loopback mode the transmit and receive data paths of the DUART can be verified. Note
that in local loopback mode, the transmit/receive interrupts are fully operational and can be controlled by
the interrupt enable register (UIER).
12.4.4
The following sections describe framing, parity, and overrun errors which may occur while data is
transferred on the UART bus. Each of the error bits are usually cleared, as described below, when the line
status register (ULSR) is read.
12.4.4.1
When an invalid STOP bit is detected, a framing error occurs and ULSR[FE] is set. Note that only the first
STOP bit is checked. In FIFO mode, ULSR[FE] is set when the character at the top of the FIFO detects a
framing error. An attempt to re-synchronize occurs after a framing error. The UART assumes that the
framing error (due to a logic 0 being read when a logic 1 (STOP) was expected) was due to a STOP bit
overlapping with the next START bit. ULSR[FE] is cleared when ULSR is read or when a new character
is loaded into the URBR from the receiver shift register.
Freescale Semiconductor
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UART divisor most significant byte register (UDMB)
UART divisor least significant byte register (UDLB)
Baud rate = (1/16) (platform clock frequency/divisor value)
Local Loopback Mode
Errors
Framing Error
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
DUART
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