MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 452

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.3.2.1
Table 10-6
govern the choices for these fields:
10-22
35–36
37–42
43–44
45–47
48–63
Bits
8–34
30
31
Bits
0–7
1. EU_SEL0 values of “No EU selected” or “Reserved” result in an “Unrecognized header” error
condition during processing of the descriptor header.
shows the values for EU_SEL0 and EU_SEL1 in the descriptor header. The following rules
Selecting Execution Units—EU_SEL0 and EU_SEL1
Name
ID_TAG
ICCR0
ICCR1
DONE
Name
DIR
DN
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-4. Header Dword Bit Definitions (continued)
Table 10-5. Header Dword Writeback Bit Definitions
Direction: direction of overall data flow:
0 Outbound
1 Inbound
This, along with the DESC_TYPE field, helps determine the sequence of actions to be
performed by the channel and selected EUs.
Done notification:
0 No done notification.
1 Signal “done” to the host on completion of this descriptor.
This enables done notification if the NT bit is set in the channel configuration register (see
Table
field of this header dword (see
(channel done interrupt enable) and CDWE (channel done writeback enable) bits in the
channel configuration register.
When “channel done writeback” is enabled, then at the completion of descriptor processing
this byte is written with the value 0xFF. “Channel done writeback” is enabled by
programming the CDWE, NT, and CDIE fields in the channel configuration register (see
Table
Reserved
when descriptor processing is complete.
00 No integrity check comparison was performed.
01 The integrity check comparison passed.
10 The integrity check comparison failed.
11 Reserved
Reserved
EU (if any) when descriptor processing is complete.
00 No integrity check comparison was performed.
01 The integrity check comparison passed.
10 The integrity check comparison failed.
11 Reserved
Reserved
Identification Tag. This value is copied from the ID_TAG field written by the host into the
fetch FIFO (see
Integrity check comparison result from primary: These bits are supplied by the primary EU
Integrity check comparison result from secondary: These bits are supplied by the secondary
10-11). The done notification can take the form of an interrupt, a writeback in the DONE
10-11).
Section 10.4.4.4, “Fetch FIFO Enqueue Register
Table
10-5), or both, depending upon the states of the CDIE
Description
Description
(FFER)”).
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