MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1307

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.4.14 Host Controller Capabilities (HOSTCAPBLT)
The host controller capabilities provides the host driver with information specific to the eSDHC
implementation. The value in this register does not change in a software reset, and any write to this register
is ignored.
Freescale Semiconductor
Reset
Reset
Offset: 0x040 (HOSTCAPBLT)
DMAS
11–12
VS18
VS30
VS33
Field
SRS
HSS
0–4
W
W
10
R
R
5
6
7
8
9
16
0
0
0
Reserved
Voltage support 1.8 V. This bit depends on the host system ability.
0 1.8 V not supported
1 1.8 V supported
Voltage support 3.0 V. This bit depends on the host system ability.
0 3.0 V not supported
1 3.0 V supported
Voltage support 3.3 V. This bit depends on the host system ability.
0 3.3 V not supported
1 3.3 V supported
Suspend/resume support. Indicates if eSDHC supports suspend/resume functionality. If this bit is 0, the
suspend and resume mechanism, as well as the read wait, are not supported and the host driver should not
issue suspend or resume commands.
0 Not supported
1 Supported
DMA support. Indicates if eSDHC is capable of using internal DMA to transfer data between system memory
and the data buffer directly.
0 DMA not supported
1 DMA supported
High speed support. Indicates if the eSDHC supports high speed mode and the host system can supply the
SD clock frequency from 25 to 50 MHz.
0 High speed supported
1 High speed supported
Reserved
0
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
0
0
Figure 20-16. Host Capabilities Register (HOSTCAPBLT)
0
0
Table 20-22. HOSTCAPBLT Field Descriptions
0
0
4
VS18 VS30 VS33 SRS DMAS HSS
0
0
5
0
0
6
7
1
0
Description
—
1
0
8
1
0
9
10
1
0
Enhanced Secure Digital Host Controller
11
0
0
—
12
0
0
13
0
0
Access: Read
MBL
14
1
0
20-33
15
31
1
0