MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1413

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

An example illustrating the H-bit in a schedule is shown in
21.6.9.4
Once the host controller has idled itself using the empty schedule detection, it naturally activates and
begins processing from the Periodic Schedule at the beginning of each micro-frame. In addition, it may
have idled itself early in a micro-frame. When this occurs (idles early in the micro-frame) the host
controller must occasionally reactivate during the micro-frame and traverse the asynchronous schedule to
determine whether any progress can be made. Asynchronous schedule Start Events are defined to be:
21.6.9.5
The operation of the empty asynchronous schedule detection feature depends on the proper management
of the Reclamation bit (RCL) in the USBSTS register. The host controller tests for an empty schedule just
after it fetches a new queue head while traversing the asynchronous schedule. The host controller sets
USBSTS[RCL] whenever an asynchronous schedule traversal Start Event occurs. USBSTS[RCL] is also
set whenever the host controller executes a transaction while traversing the asynchronous schedule.The
host controller clears USBSTS[RCL] whenever it finds a queue head with its H-bit set. Software should
only set a queue head's H-bit if the queue head is in the asynchronous schedule. If software sets the H-bit
in an interrupt queue head, the resulting behavior is undefined. The host controller may clear
USBSTS[RCL] when executing from the periodic schedule.
21.6.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads
This section presents an overview of how the host controller interacts with queuing data structures.
Freescale Semiconductor
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AsyncListAddr
Operational
Whenever the host controller transitions from the periodic schedule to the asynchronous schedule.
If the periodic schedule is disabled and the asynchronous schedule is enabled, then the beginning
of the micro-frame is equivalent to the transition from the periodic schedule, or
The asynchronous schedule traversal restarts from a sleeping state.
USBCMD
Registers
USBSTS
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•
•
•
•
•
Figure 21-49. Asynchronous Schedule List with Annotation to Mark Head of List
Asynchronous Schedule Traversal: Start Event
Reclamation Status Bit (USBSTS Register)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
H
1
Horizontal Ptr
Reclamation Flag
List Head
Operational
Area
Typ T
01
1: Transaction Executed
0: Head of List Seen
0
Asynchronous Schedule
H
0
Horizontal Ptr
Operational
Figure 21-49
Area
Typ T
01 0
H
0
Horizontal Ptr
Universal Serial Bus Interfaces
Operational
Area
Typ T
01 0
21-79