MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 82

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table
Number
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-35
4-36
4-37
4-38
4-39
4-40
5-1
5-2
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
lxxxii
eTSEC1 Width Configuration ............................................................................................... 4-20
eTSEC3 Width Configuration ............................................................................................... 4-20
eTSEC1 Protocol Configuration ........................................................................................... 4-21
eTSEC3 Protocol Configuration ........................................................................................... 4-21
PCI Clock Select ................................................................................................................... 4-22
PCI Speed Configuration ...................................................................................................... 4-22
PCI I/O Impedance................................................................................................................ 4-22
PCI Arbiter Configuration .................................................................................................... 4-23
Memory Debug Configuration.............................................................................................. 4-23
DDR Debug Configuration ................................................................................................... 4-23
General-Purpose POR Configuration.................................................................................... 4-24
Engineering Use POR Configuration.................................................................................... 4-24
High Speed Interface Clocking ............................................................................................. 4-25
SD/MMC Card Data Structure.............................................................................................. 4-29
Config Address Field Description, CNT = 0 ........................................................................ 4-31
Config Address Field Description, CNT = 1 ........................................................................ 4-32
eSPI EEPROM Data Structure.............................................................................................. 4-37
Config Address Field Description, CNT = 0 ........................................................................ 4-39
Config Address Field Description, CNT = 1 ........................................................................ 4-39
Differences Between the e500 Core and the PowerQUICC III Core Implementation .......... 5-4
Device Revision Level Cross-Reference ................................................................................ 5-6
Available L2 Cache/SRAM Configurations............................................................................ 6-3
Way Selection for SRAM Accesses........................................................................................ 6-6
L2/SRAM Memory-Mapped Registers................................................................................... 6-9
L2CTL Field Descriptions .................................................................................................... 6-10
L2CEWARn Field Descriptions............................................................................................ 6-14
L2CEWAREAn Field Descriptions ...................................................................................... 6-14
L2CEWCRn Field Descriptions............................................................................................ 6-15
L2SRBARn Field Descriptions............................................................................................. 6-16
L2SRBAREAn Field Descriptions ....................................................................................... 6-17
L2ERRINJHI Field Description............................................................................................ 6-18
L2ERRINJLO Field Description .......................................................................................... 6-19
L2ERRINJCTL Field Descriptions....................................................................................... 6-19
L2CAPTDATAHI Field Description..................................................................................... 6-20
L2CAPTDATALO Field Description.................................................................................... 6-20
L2CAPTECC Field Descriptions .......................................................................................... 6-21
L2ERRDET Field Descriptions ............................................................................................ 6-21
L2ERRDIS Field Descriptions.............................................................................................. 6-22
L2ERRINTEN Field Descriptions ........................................................................................ 6-23
L2ERRATTR Field Descriptions .......................................................................................... 6-23
L2ERRADDRL Field Description........................................................................................ 6-24
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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