MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 552

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.5.5
The KEU status register, shown in
outputs. While writing to this location, an address error is reflected in the KEU interrupt status register.
Table 10-55
10-122
Bits
62
63
40–47
48–55
56–57
0–39
Bits
58
Reset
Field
Addr
R/W
Name
SR
RI
describes the KEU status register fields.
KEU Status Register (KEUSR)
0
Name
HALT
OFL
Re- Initialization.
It is same as software reset (SR), except that the interrupt mask register remains unchanged. Completion of
re-initialization is indicated by the RESET_DONE bit in the KEU status register.
0 Normal operation
1 Re-initialize the KEU
Software reset.
Functionally equivalent to hardware reset (the RESET signal), but only for the KEU. All registers and internal
state are returned to their defined reset state. Upon negation of the SR bit, the KEU enters a routine to perform
proper initialization of the parameter memories. The reset done (RD) bit in the KEU status register indicates
when this initialization is complete
0 Normal operation
1 Full KEU reset
IFL
—
—
Table 10-54. KEU Reset Control Register Field Descriptions (continued)
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Output FIFO level. The number of dwords currently in the output FIFO.
Input FIFO level. The number of dwords currently in the input FIFO.
Reserved
Indicates when the KEU core has halted due to an error.
0 KEU not halted
1 KEU core halted (must be reset/re-initialized)
Note: As the error causing the KEU to stop operating may be masked to the interrupt status register,
39
Table 10-55. KEU Status Register Fields Description
the status register is used to provide a second source of information regarding errors
preventing normal operation.
40
OFL
Figure
Figure 10-68. KEU Status Register
47
10-68, is a read-only register that reflects the state of six status
48
IFL
KEU 0x3_E028
55
Description
R
0
Description
56
—
57
HALT
58
59
ICCR
60
Freescale Semiconductor
61
EI
DI
62
RD
63