MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 196

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
For any SerDes that is not disabled through cfg_io_ports[0:2]=001 or cfg_srds2_prtcl[0:2]=111
respectively, the applicable SDn_REF_CLK/SDn_REF_CLK must be constantly driven, even when in
Deep Sleep mode, in order to avoid loss of lock.
4.4.4.2.1
Section 4.4.3.8, “SerDes1 I/O Port
options. Note that the CCB clock frequency must be considered for proper operation of such interfaces as
described below.
For proper PCI Express operation, the CCB clock frequency must be greater than or equal to:
See
Note that the minimum CCB:SYSCLK ratio for PCI in synchronous mode is 6:1. See
“System PLL
4.4.4.3
The Ethernet blocks operate asynchronously with respect to the rest of the device. These blocks use receive
and transmit clocks supplied by their respective PHY chips, plus a 125-MHz clock input for gigabit
protocols. Data transfers are synchronized to the CCB clock internally.
4.4.4.4
As shown in
facilities. RTC can also be used (optionally) by the programmable interrupt controller (PIC) global timer
facilities. The RTC is separate from the e500 core clock and is intended to support relatively low frequency
timing applications. The RTC frequency range is specified in the MPC8536E Integrated Processor
Hardware Specifications, but the maximum value should not exceed one-quarter of the CCB Frequency.
Before being distributed to the core time base, RTC is sampled and synchronized with the CCB clock.
The clock source for the core time base is specified by two fields in HID0: time base enable (TBEN), and
select time base clock (SEL_TBCLK). If the time base is enabled, (HID0[TBEN] is set), the clock source
is determined as follows:
The default source of the time base is the CCB clock divided by eight. For more details, see the PowerPC
e500 Core Complex Reference Manual.
Section 9.3.2.6, “Timer Control Registers
the RTC signal to clock the global timers in the PIC unit.
4-26
•
•
Section 17.1.3.2, “Link
HID0[SEL_TBCLK] = 0, the time base is updated every 8 CCB clocks
HID0[SEL_TBCLK] = 1, the time base is updated on the rising edge of RTC
Figure
Ethernet Clocks
Real Time Clock
Ratio,” for details of selecting this ratio.
Minimum Frequency Requirements
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
4-7, the real time clock (RTC) input can optionally be used to clock the e500 core timer
Width,” for PCI Express interface width details.
527 MHz
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Selection,” describes various high-speed interface configuration
(TCRA–TCRB),” provides additional information on the use of
PCI Express link width
8
Freescale Semiconductor
Section 4.4.3.1,