MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 215

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5
e500 Core Integration Details
This chapter descibes how the core is integrated into the SoC.
Core Complex Bus
that discuss functionality in which core and SoC operations interact. Such topics include reset, power
management, interrupt management, and debug.
This chapter also lists SoC-specific details of the core’s programming model. For example, the e500
programming model defines the processor version register (PVR) and system version register (SVR),
special-purpose registers (SPRs) that respectively identify the version and revision of the core and of the
integrated device. These values are provided in
additional links are provided to other chapters that provide a context for a discussion of these registers.
The section
programming model that have SoC-specific behavior that cannot be fully understood by reading the e500
Reference Manual alone.
General information about e500 core functionality can be found in the following documention:
5.1
Figure 5-1
independently and in parallel. Note that this is a conceptual diagram that does not attempt to show how
these features are physically implemented.
Freescale Semiconductor
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Chapter 5, “e500 Core Integration
The PowerPC™ e500 Core Family Reference Manual (referrred to here as the e500 Reference
Manual) provides detailed information about the functions and features of the core, and in
particular it describes details of how architecture-defined features are implemented.
The “e500 Core Complex Bus (CCB) and System Integration” chapter in the e500 Reference
Manual describes core-to-SoC integration issues from the perspective of the e500 core.
The EREF: A Programmer’s Reference Manual for Freescale Embedded Processors (Including the
e200 and e500 Families) describes in detail features defined by the Power ISA and Freescale EIS
(referred to generically as the architecture). Unless otherwise stated in the e500 Reference Manual,
e500 features are implemented as the are defined by the architecture and described in the EREF.
How the integrated device implements e500 core features, including specific registers and register
fields, is summarized in
is a block diagram of the processor core complex that shows how the functional units operate
e500 Core Overview
“Register Model Integration Details”
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(CCB),” describes hardware aspects of that integration and provides links to chapters
Section 5.3, “Summary of Core Integratation Details.”
Details,” includes a general summary of e500 core features.
Section 5.3, “Summary of Core Integratation
in
Table 5-1
Section 5.2, “e500 Core Integration and the
describes a few aspects of the core
Details,” and
5-1