MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 699

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.4.2.4
External access termination is supported by the GPCM using the asynchronous LGTA input signal, which
is synchronized and sampled internally by the local bus. If, during assertion of LCSn, the sampled LGTA
signal is asserted, it is converted to an internal generation of transfer acknowledge, which terminates the
current GPCM access (regardless of the setting of ORn[SETA]). LGTA should be asserted for at least one
Freescale Semiconductor
LBCTL
LBCTL
LCLK
LCLK
LCS n
LCS n
LALE
LCSy
LALE
LCSy
LAD
LOE
Figure 13-43. GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing)
LAD
LOE
TA
TA
External Access Termination (LGTA)
A
A
Rd. Address
Address 1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(TRLX = 0, EHTR = 1, One-Cycle Extended Hold Time on Reads)
Figure 13-44. GPCM Read Followed by Write
Latched Read Address
Latched Address 1
Read Data 1
Read Data
Bus turnaround
Extended hold
Bus turnaround
Address 2
Wr. Address
Latched Address 2
Enhanced Local Bus Controller
Wr. Address
Wr. Data
Data 2
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