MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1122

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
Figure 17-19
17.3.5.2.3
The PCI Express inbound translation address registers, shown in
internal platform address to be used. Note that PEXITAR0 does not exist in the memory-mapped space; it
is a fixed 1-Mbyte translation to the internal configuration (CCSRBAR) space.
Table 17-19
17-26
Offset Window 1: 0xDE0
Reset
12–31
8–11
Bits
0–7
W
R
Window 2: 0xDC0
Window 3: 0xDA0
0
To Memory
Name
TEA
TA
—
Table 17-19. PCI Express Inbound Translation Address Registers Field Descriptions
describes the fields of the PCI Express inbound translation address registers.
shows the inbound transaction flow in RC mode.
Figure 17-20. PCI Express Inbound Translation Address Registers (PEXITAR n )
PCI Express Inbound Translation Address Registers (PEXITAR n )
Reserved
Translation extended address. Target address which indicates the starting point of the inbound translated
address. The translation address must be aligned based on the size field. Corresponds to internal platform
address bits [0:3] where bit 0 is the msb of the internal platform address.
Translation address. Target address which indicates the starting point of the inbound translated address. The
translation address must be aligned based on the size field. This corresponds to internal platform address
bits [4:23].
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Inbound ATMUs
7
Figure 17-19. RC Inbound Transaction Flow
8
TEA
11 12
Memory or IO Base
Memory or IO Limit
Memory Base
Primary Side
Memory Limit
Prefetchable
Prefetchable
All zeros
Description
Figure
17-20, contain the translated
TA
Secondary Side
Freescale Semiconductor
Access: Read/Write
31