MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 46

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
21.7.1.1
21.7.1.2
21.7.1.3
21.7.1.4
21.7.2
21.8
21.8.1
21.8.2
21.8.2.1
21.8.2.2
21.8.2.2.1
21.8.2.2.2
21.8.2.2.3
21.8.3
21.8.3.1
21.8.3.1.1
21.8.3.2
21.8.3.2.1
21.8.3.2.2
21.8.3.3
21.8.3.3.1
21.8.3.3.2
21.8.3.4
21.8.3.4.1
21.8.3.5
21.8.3.5.1
21.8.3.5.2
21.8.3.5.3
21.8.3.5.4
21.8.3.6
21.8.3.6.1
21.8.3.6.2
21.8.4
21.8.4.1
21.8.4.2
21.8.5
21.8.5.1
21.8.5.2
21.8.5.3
21.8.5.4
21.8.5.5
xlvi
Device Operational Model......................................................................................... 21-122
Endpoint Transfer Descriptor (dTD) ..................................................................... 21-120
Device Controller Initialization ............................................................................. 21-122
Port State and Control............................................................................................ 21-123
Managing Endpoints .............................................................................................. 21-126
Managing Queue Heads......................................................................................... 21-136
Managing Transfers with Transfer Descriptors ..................................................... 21-138
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Endpoint Capabilities/Characteristics................................................................ 21-118
Transfer Overlay ................................................................................................ 21-119
Current dTD Pointer .......................................................................................... 21-119
Set-up Buffer...................................................................................................... 21-119
Bus Reset ........................................................................................................... 21-125
Suspend/Resume................................................................................................ 21-126
Endpoint Initialization ....................................................................................... 21-127
Data Toggle........................................................................................................ 21-128
Device Operational Model For Packet Transfers .............................................. 21-129
Interrupt/Bulk Endpoint Operational Model ..................................................... 21-130
Control Endpoint Operation Model ................................................................... 21-132
Isochronous Endpoint Operational Model......................................................... 21-134
Queue Head Initialization .................................................................................. 21-137
Operational Model for Setup Transfers ............................................................. 21-137
Software Link Pointers ...................................................................................... 21-138
Building a Transfer Descriptor .......................................................................... 21-138
Executing a Transfer Descriptor ........................................................................ 21-139
Transfer Completion .......................................................................................... 21-139
Flushing/De-Priming an Endpoint ..................................................................... 21-140
Suspend Description ...................................................................................... 21-126
Suspend Operational Model .......................................................................... 21-126
Resume .......................................................................................................... 21-126
Stalling ........................................................................................................... 21-127
Data Toggle Reset.......................................................................................... 21-128
Data Toggle Inhibit ........................................................................................ 21-128
Priming Transmit Endpoints.......................................................................... 21-129
Priming Receive Endpoints ........................................................................... 21-129
Interrupt/Bulk Endpoint Bus Response Matrix ............................................. 21-131
Setup Phase.................................................................................................... 21-132
Data Phase ..................................................................................................... 21-132
Status Phase ................................................................................................... 21-133
Control Endpoint Bus Response Matrix ........................................................ 21-133
Isochronous Pipe Synchronization ................................................................ 21-135
Isochronous Endpoint Bus Response Matrix................................................. 21-136
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