MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 204

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
4.5.1.1.6
If at any stage the boot loader code detects an error and cannot continue, it will disable the eSDHC and
will issue a hardware reset request of the SoC by setting RSTCR[HRESET_REQ]. This may occur in any
of the following scenarios:
The boot loader code supports redundancy, which allows boot to succeed even in the presence of SD/MMC
bad blocks. It does this by searching for the BOOT signature in up to 24 locations, and trying the next block
if the BOOT signature is not found, or if a read CRC error is found. Each location tried is at a fixed offset
of 512 bytes (0x200) from the previous (unsuccessful) offset, irrespective of the actual block size of the
SD/MMC card.
For reference, the following diagram gives an example SD/MMC memory card data structure which can
be used for maximum SD/MMC card data redundancy.
Note that if 0x40+8*(N–1)+4>=0x200 (where N is the number of Configuration Words), then care needs
to be taken to ensure that the configuration words at 0x40+i*0x200 (for all 2<=i<=24) must not contain
the BOOT signature. This ensures that the boot loader code does not mistakenly detect a BOOT signature.
This also reduces the number of copies of boot code that can be used on one device.
4-34
7. Based on the values returned from the SD/MMC card’s CSD register, the eSDHC’s registers are
8. The eSDHC begins reading the SD/MMC data structure from the card.
9. The eSDHC begins fetching the user code from the card.
10. If either the BOOT signature is not found at memory offset 0x40, or if when reading the Control
11. The processor core waits until the user code DMA transfer is complete.
12. The processor core jumps to the Execution Starting Address to begin execution of the user’s code.
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updated to reflect the maximum clock frequency jointly supported by the eSDHC controller, and
the SD/MMC card connected to it.
and Configuration Words or the User’s Code a read CRC error is detected, then it may be due to a
bad block on the SD/MMC memory card. To counteract this and provide error resilience, if this
occurs the eSDHC returns to step 8, fetching data from an address 0x200 greater than the
previously fetched address. For example, if there have been i failed attempts, then on the following
try the BOOT signature is checked at offset 0x40+i*0x200. If this sequence fails 24 times, then the
system boot is deemed to have failed.
BOOT signature not found at offset 0x40 or CRC error on any of the data read by the eSDHC 24
times.
Timeout while waiting for the SD/MMC card to respond at any stage.
No card inserted.
Incorrect type of card inserted that is not supported for boot (such as CE-ATA).
There is no common protocol, voltage or frequency mutually supported by the SD/MMC card and
the eSDHC.
The eSDHC reads as far as the Source Address (specified by the Control Word of the SD/MMC
data structure) without seeing a EC=1 Configuration Word.
eSDHC Boot Error Handling
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor