MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 644

BOARD DEV SYSTEM MPC8536E

MPC8536DS

Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets

Specifications of MPC8536DS

Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Enhanced Local Bus Controller
13.1.1
The main component of the eLBC is its memory controller, which provides a seamless interface to many
types of memory devices and peripherals. The memory controller is responsible for controlling eight
memory banks shared by a GPCM, an FCM, and up to three UPMs. As such, it supports a minimal glue
logic interface to SRAM, EPROM, NOR Flash EEPROM, NAND Flash EEPROM, burstable RAM,
regular DRAM devices, extended data output DRAM devices, and other peripherals. The external address
latch signal (LALE) allows multiplexing of addresses with data signals to reduce the device pin count.The
eLBC also includes a number of data checking and protection features such as data parity generation and
checking, write protection and a bus monitor to ensure that each bus cycle is terminated within a
user-specified period.
13.1.2
The eLBC main features are as follows:
13-2
Memory controller with eight memory banks
— 32-bit address decoding with mask
— Variable memory block sizes (32 Kbytes to 4 Gbytes)
— Selection of control signal generation on a per-bank basis
— Data buffer controls activated on a per-bank basis
— Automatic segmentation of large transactions into memory accesses optimized for bus width
— Odd/even parity checking including read-modify-write (RMW) parity for single accesses
— Write-protection capability
— Atomic operation
— Parity byte-select
General-purpose chip-select machine (GPCM)
— Compatible with SRAM, EPROM, NOR Flash EEPROM, and peripherals
— Global (boot) chip-select available at system reset
— Boot chip-select support for 8-, 16-, and 32-bit devices
— Minimum three-clock access to external devices
— Four byte-write-enable signals (LWE[0:3])
— Output enable signal (LOE)
— External access termination signal (LGTA)
NAND Flash control machine (FCM)
— Compatible with small (512+16 bytes) and large (2048+64 bytes) page parallel NAND Flash
— Global (boot) chip-select available at system reset, with 4-Kbyte boot block buffer for
— ECC checking enable/disable feature supported during boot
and addressing capability
EEPROM
execute-in-place boot loading
Overview
Features
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor

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