MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1581

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UART0 baud rate
UART1 baud rate
PMC0 carry-out
PMC1 carry-out
PMC2 carry-out
PMC3 carry-out
PMC4 carry-out
PMC5 carry-out
PMC6 carry-out
PMC7 carry-out
PMC8 carry-out
PMC9 carry-out
24.4.8
Table 24-12
The settings in
For simple event counting, a non-threshold event is selected in PMLCAn[EVENT] and all other features
are disabled by clearing all register fields except for CE.
For the triggering example any event can be selected in PMLCAn[EVENT]. All other features are disabled
by clearing these register fields except for CE to allow interrupt signalling. If PMLCBn[TRIGONSEL] is
Freescale Semiconductor
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Simple event performance monitoring example
Triggering event performance monitoring example
Threshold event performance monitoring example
Burstiness event performance monitoring example
Event Counted
Performance Monitor Examples
contains sample register settings for the four supported modes.
PMGC0[FCECE]
PMGC0[PMIE]
PMGC0[FAC]
PMLCA n [CE]
Table 24-11
PMLCA n [FC]
Field
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 24-10. Performance Monitor Events (continued)
are identical for all four examples.
Setting
Table 24-11. PMGC0 and PMLCA n Settings
0
1
1
0
1
Counters must not be frozen.
Performance monitor interrupts are enabled
Counters should be frozen when an interrupt is signalled.
Counters cannot be frozen for counting.
Overflow condition enable is required to allow interrupt signalling.
Number
C1:127
C5:127
Ref:10
Ref:1
Ref:2
Ref:3
Ref:4
Ref:5
Ref:6
Ref:7
Ref:8
Ref:9
Chaining Events
—
—
PMC0[0] 1-to-0 transitions.
PMC1[0] 1-to-0 transitions. Reserved for PMC1.
PMC2[0] 1-to-0 transitions. Reserved for PMC2.
PMC3[0] 1-to-0 transitions. Reserved for PMC3.
PMC4[0] 1-to-0 transitions. Reserved for PMC4.
PMC5[0] 1-to-0 transitions. Reserved for PMC5.
PMC6[0] 1-to-0 transitions. Reserved for PMC6.
PMC7[0] 1-to-0 transitions. Reserved for PMC7.
PMC8[0] 1-to-0 transitions. Reserved for PMC8.
PMC9[0] 1-to-0 transitions. Reserved for PMC9.
Reason
Description of Event Counted
Device Performance Monitor
24-27