MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 408

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
9.3.6.3
MSIIR, shown in
is written, MSIIR[SRS] selects the register in which an interrupt bit is to be set; MSIIR[IBS] selects the
shared interrupt field in the selected MSIR register to be set. MSIIR is primarily intended to support PCI
Express MSIs.
Table 9-35
9.3.6.4
The MSIVPRs, shown in
“Flow of Interrupt Control,”
9-38
Offset MSIVPR0: 0x1C00; MSIVPR1: 0x1C20; MSIVPR2: 0x1C40; MSIVPR3: 0x1C60; MSIVPR4:
Reset
Offset 0x1740
Reset
W
R
W
R
0x1C80; MSIVPR5: 0x1CA0; MSIVPR6: 0x1CC0; MSIVPR7: 0x1CE0
MSK
1
0
0
SRS
describes the bits of the MSIIR.
Figure 9-34. Shared Message Signaled Interrupt Vector/Priority Register (MSIVPRs)
A
1
0
Shared Message Signaled Interrupt Index Register (MSIIR)
Shared Message Signaled Interrupt Vector/Priority Register (MSIVPRs)
2
0
Figure
3
Figure 9-33. Shared Message Signaled Interrupt Index Register (MSIIR)
8–31
Bits
0
0–2
3–7
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
IBS
9-32, provides the mechanism for setting an interrupt in the MSIRs. When MSIIR
0
Name
SRS
Figure
IBS
—
0
—
for information on IPR and ISR.
7
0
Shared interrupt register select. Selects the MSIR to be written
000 MSIR 0
001 MSIR 1
010 MSIR 2
...
111 MSIR 7
Interrupt bit select—Selects the bit to set in the MSIR
00000 Set field SH0 (bit 31)
00001 Set field SH1 (bit 30)
00010 Set field SH2 (bit 29)
...
11111 Set field SH31 (bit 0)
Reserved, should be cleared.
9-34, have the same fields and format as the GTVPRs. See
8
0
Table 9-35. MSIIR Field Descriptions
0
0
11 12
0
0
PRIORITY
0
0
All zeros
Description
15 16
0
0
0
0
0
—
0
0
0
VECTOR
0
0
Freescale Semiconductor
0
Access: Write Only
0
Section 9.4.1,
0
Access: Mixed
0
0
0
31
31
0