MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1593

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 25-7
Freescale Semiconductor
21–23
24–31
7–20
Bits
0
1
2
3
4
5
6
NECEN Not equal context enable. Qualifies the matching of current context with programmed context as a watchpoint
SIDEN Source ID enable
TIDEN Target ID enable
ECEN Equal context enable. Qualifies the matching of current context with programmed context as a watchpoint
Name
STRT Start condition. Specifies the event that arms the watchpoint monitor to start looking for the programmed
AMD
TMD
EN
—
—
describes WMCR0 fields.
Enable
0 Watchpoint monitor events are not flagged.
1 A watchpoint monitor event is flagged.
Address match disable. Qualifies address match as a watchpoint event criterion.
0 Address matching is used to recognize a watchpoint event.
1 Address matching does not affect watchpoint event detection.
Transaction match disable. Qualifies transaction type match (as defined in WMCR1[IFSEL] and WMTMR) as
a watchpoint event criterion.
0 A transaction type match is used to recognize watchpoint events.
1 A transaction type match does not affect watchpoint event detection.
event criterion, as written in the context registers described in
0 Current context match does not affect watchpoint event detection.
1 Watchpoint events are qualified by comparing current context with the programmed context event value.
Note: ECEN and NECEN must not be enabled in the same run. If both are set, watchpoint events are
event criterion, as written in the context registers described in
0 The failure of a current context match does not affect watchpoint event detection
1 Watchpoint events are qualified with NOT getting a current context compare with the programmed context
Note: ECEN and NECEN must not be enabled in the same run. If both are set, watchpoint events are
0 Source ID does not affect watchpoint event detection.
1 Watchpoint events are qualified by comparison with the programmed WMCR1(SID) value.
0 Target ID does not affect watchpoint event detection.
1 Watchpoint events are qualified by comparison with the programmed WMCR1(TID) value.
Reserved
event.
000 No event. Armed immediately
001 Trace buffer event is detected
010 Performance monitor signals overflow
011 TRIG_IN transitions from 0 to 1
100 TRIG_IN transitions from 1 to 0
101 Current context ID equals programmed context ID
110 Current context ID is not equal to programmed context ID
111 Reserved
Reserved
event value.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
inhibited (never occur).
inhibited (never occur).
Table 25-7. WMCR0 Field Descriptions
Description
Section 25.3.3, “Context ID Registers.”
Section 25.3.3, “Context ID Registers.”
Debug Features and Watchpoint Facility
25-11