MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 785

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The different interface configurations indicated by registers ECNTRL and MACCFG2 are summarized in
Table
14.5.3.1.7
PTV is a 32-bit register written by the user to store the pause duration used when the eTSEC initiates an
IEEE 802.3 PAUSE control frame through TCTRL[TFC_PAUSE]. The low-order 16 bits (PT) represent
the pause time and the high-order 16 bits (PTE) represent the extended pause control parameter. The pause
time is measured in units of pause_quanta, equal to 512 bit times. The pause time can range from 0 to
65,535 pause_quanta, or 0 to 33,553,920 bit times. See
details.
Freescale Semiconductor
Bits
30
31
14-12.
1
FIFO 8-bits
TBI 1Gbps
RTBI 1Gbps
GMII 1Gbps
RGMII 1Gbps
RGMII 100 Mbps
RGMII 10 Mbps
MII 10/100 Mbps
RMII 100 Mbps
RMII 10 Mbps
SGMII 1 Gbps
SGMII 100 Mbps
SGMII 10 Mbps
Figure 14-8
See MII 10/100 Mbps mode for GMII 10/100 Mbps ‘fall-back’ mode.
Interface Mode
SGMIIM
Name
—
Pause Time Value Register (PTV)
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Serial GMII mode. If this bit is set, a SGMII pin interface is expected to be connected via an on chip
SerDes.
This register can be pin-configured at reset to 0 or 1. See
Configuration.”
0 SGMII mode disabled. eTSEC connected via a parallel interface.
1 SGMII mode enabled.
Reserved
describes the definition for the PTV register.
FIFM
Table 14-11. ECNTRL Field Descriptions (continued)
1
0
0
0
0
0
0
0
0
0
0
0
0
Table 14-12. eTSEC Interface Configurations
GMIIM
0
0
0
1
1
1
1
0
0
0
0
0
0
TBIM
0
1
1
0
0
0
0
0
0
0
1
1
1
ECNTRL Field
RPM
1
0
1
0
1
1
1
0
0
0
0
0
0
Section 14.6.3.9, “Flow Control,”
Description
R100M
0
0
0
0
0
1
0
0
1
0
0
1
0
Section 4.4.3, “Power-On Reset
RMM
0
0
0
0
0
0
0
0
1
1
0
0
0
Enhanced Three-Speed Ethernet Controllers
SGMIIM
0
0
0
0
0
0
0
0
0
0
1
1
1
MACCFG2 Field
I/F Mode
10
10
10
10
01
01
01
01
01
10
01
01
—
for additional
14-37