MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 827

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.3.5.4
The HAFDUP register is written by the user.
Table 14-46
Freescale Semiconductor
16–19
20–25
26–31
Offset eTSEC1:0x2_450C;
Reset
Reset
8–11
Bits
0–7
12
13
14
15
W
W
R
R
eTSEC3:0x2_650C
Collision Window This is a programmable field representing the slot time or collision window during which collisions
Retransmission Maximum
Retransmission
16
0
0
1
Alternate BEB
Excess Defer
No BackOff
Truncation
Maximum
BackOff
Alt BEB
describes the fields of the HAFDUP register.
BP No
Name
—
—
Half-Duplex Register (HAFDUP)
0
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
1
Reserved
This field is used while ALTERNATE BINARY EXPONENTIAL BACKOFF ENABLE is set. The
value programmed is substituted for the Ethernet standard value of ten. Its default is 0xA.
Alternate binary exponential backoff. This bit is cleared by default.
0 The Tx MAC follows the standard binary exponential back off rule.
1 The Tx MAC uses the ALTERNATE BINARY EXPONENTIAL BACKOFF TRUNCATION setting
Back pressure no backoff. This bit is cleared by default.
0 The Tx MAC follows the binary exponential back off rule.
1 The Tx MAC immediately re-transmits, following a collision, during back pressure operation.
No backoff. This bit is cleared by default.
0 The Tx MAC follows the binary exponential back off rule.
1 The Tx MAC immediately re-transmits following a collision.
Excessively deferred. This bit is set by default.
0 The Tx MAC aborts the transmission of a packet that is excessively deferred.
1 The Tx MAC allows the transmission of a packet that is excessively deferred.
This is a programmable field specifying the number of retransmission attempts following a collision
before aborting the packet due to excessive collisions. The standard specifies the attempt limit to
be 0xF (15d). Its default value is 0xF.
Reserved
occur in properly configured networks. Because the collision window starts at the beginning of
transmission, the preamble and SFD are included. Its default of 0x37 (55d) corresponds to the
count of frame bytes at the end of the window.
—
instead of the 802.3 standard tenth collision. The standard specifies that any collision after the
tenth uses one less than 210 as the maximum backoff time.
19
0
1
Figure 14-42. Half-Duplex Register Definition
Table 14-46. HAFDUP Field Descriptions
20
0
0
0
0
0
0
—
0
0
7
Figure 14-42
Alternate BEB
8
1
0
Truncation
25
0
0
26
1
1
11
0
1
describes the HAFDUP register.
Description
Alt BEB BP No BackOff No BackOff Excess Defer
12
0
0
Enhanced Three-Speed Ethernet Controllers
Collision Window
13
0
1
14
0
1
Access: Read/Write
15
31
1
1
14-79