MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1553

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
lock. Additionally, the user will need to set the reset counter RCNT in the PMRCCR register to ensure
there is enough time for the e500 PLL to lock.
23.5.1.16.2 POWER_EN Output Signal
POWER_EN signal is an external output from the power management controller that indicates to the
external power regulator to toggle the power switch to on mode.
This signal is asserted when the system is in deep sleep mode and a wake-up event was accepted, but only
after the counter of PMCCR[PDCNT] has finished counting. The signal deasserts after power is restored
(POWER_OK is asserted and/or the voltage ramp-up counter VRCNT expires).
Assertion of POWER_EN signals the external power regulator to toggle the power switch on; its negation
signals the regulator to toggle the power switch off. Assertion may occur only when a wakeup event
occurs. Negation indicates no wakeup event occurs to the device.
The timing of POWER_EN is asynchronous; it is stable long enough so it is possible to synchronize it.
23.5.1.16.3 DPSLP Register Bit
The POWMGTCSR[DPSLP] bit is set when the user wants to remove power to a portion of the die in deep
sleep mode. This bit is cleared automatically by hardware upon receiving a wake up interrupt from the
OpenPIC.
The
Section 23.5.1.8, “Power-Down Sequence Coordination,”
and
Section 23.5.1.13, “Requirements for
Reaching and Recovering from Deep Sleep State,”
provide other important details on deep sleep mode.
23.5.1.16.4 RST_DPSLP Register Bit
The AUTORSTSR[RST_DPSLP] bit is set when the core complex is reset in response to a deep sleep
wake up event. This bit also allows boot code to distinguish between POR boot (cold reset) and boot from
deep sleep (warm reset); this bit is cleared by the boot code. This register bit is referenced relative to the
CCSRBAR register value. If the CCSRBAR register is modified from its default location (the MPC8536E
configuration registers are moved to a different location in memory), boot software must take care to
ensure it can still find the AUTORSTSR[RST_DPSLP] bit. It may be necessary before entering deep sleep
to change the CCSRBAR register back to its default location.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor
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