MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1417

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.6.11 Ping Control
USB 2.0 defines an addition to the protocol for high-speed devices called Ping. Ping is required for all USB
2.0 High-speed bulk and control endpoints. Ping is not allowed for a split-transaction stream. This
extension to the protocol eliminates the bad side-effects of Naking OUT endpoints. The Status field has a
Ping State bit, which the host controller uses to determine the next actual PID it will use in the next
transaction to the endpoint (see
queue heads that meet all of the following criteria:
Table 21-66
PING protocol. Refer to Chapter 8 in the USB Specification, Revision 2.0 for detailed description on the
Ping protocol.
The Ping State bit is described in
on the initialization of the ping protocol (that is, start in Do OUT when we don't know whether there is
space on the device or not). The host controller manages the Ping State bit. System software sets the initial
value in the queue head when it initializes a queue head. The host controller preserves the Ping State bit
across all queue advancements. This means that when a new qTD is written into the queue head overlay
area, the previous value of the Ping State bit is preserved.
Freescale Semiconductor
•
•
•
The queue head is not an interrupt
The EPS field equals High-Speed
The PIDCode field equals OUT
illustrates the state transition table for the host controller's responsibility for maintaining the
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
1
2
3
Transaction Error (XactErr) is any time the host misses the handshake.
No transition change required for the Ping State bit. The Stall handshake
results in the endpoint being halted (for example, Active cleared and Halt
set). Software intervention is required to restart queue.
A Nyet response to an OUT means that the device has accepted the data,
but cannot receive any more at this time. Host must advance the transfer
state and additionally, transition the Ping State bit to Do Ping.
Current
Do OUT
Do OUT
Do OUT
Do OUT
Do OUT
Do Ping
Do Ping
Do Ping
Do Ping
Table 21-66. Ping Control State Transition Table
Table
Table
21-53). The Ping State bit is only managed by the host controller for
PING
PING
PING
PING
Host
OUT
OUT
OUT
OUT
OUT
21-53. The defined ping protocol allows the host to be imprecise
Event
XactErr
XactErr
Device
Stall
Nyet
Stall
Nak
Ack
Nak
Ack
1
1
Do Ping
Do Ping
Do OUT
Do Ping
Do Ping
Do OUT
Do Ping
Next
N/C
N/C
2
2
3
Universal Serial Bus Interfaces
21-83