MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1113

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17-11
Freescale Semiconductor
Offset 0x028
Reset
Reset
23–24
0–15
Bits
16
17
18
19
20
21
22
25
26
W
W
R
R PTO
Figure 17-9. PCI Express PME and Message Interrupt Enable Register (PEX_PME_MES_IER)
16
IE
ENL23IE Entered L2/L3 ready interrupt enable. When set and PEX_PME_MES_DR[ENL23]=1 generates an
EXL23IE Exited L2/L3 ready interrupt enable. When set and PEX_PME_MES_DR[EXL23]=1 generates an
0
AIONIE
HRDIE
PTOIE
LDDIE
Name
AIBIE
—
—
—
—
shows the fields of the PCI Express PME and message interrupt enable register.
—
17
Reserved
PME turn off interrupt enable. When set and PEX_PME_MES_DR[PTO]=1 generates an interrupt.
1 Enable PME_Turn_Off_message interrupt generation
0 Disable PME_Turn_Off message interrupt generation
Reserved
interrupt.
1 Enable Entered_L2/L3 ready state interrupt generation
0 Disable Entered_L2/L3 ready state interrupt generation
interrupt.
1 Enable Exited_L2/L3 ready state interrupt generation
0 Disable Exited_L2/L3 ready state interrupt generation
Reserved
Hot reset detected interrupt enable. When set and PEX_PME_MES_DR[HRD]=1 generates an interrupt.
1 Enable hot reset state interrupt generation
0 Disable hot reset state interrupt generation
Link down detected interrupt enable. When set and PEX_PME_MES_DR[LDD]=1 generates an interrupt.
1 Enable link down state interrupt generation
0 Disable link down state interrupt generation
Reserved
Attention indicator on interrupt enable. When set and PEX_PME_MES_DR[AION]=1 generates an
interrupt.
1 Enable attention indicator on message interrupt generation
0 Disable attention indicator on message interrupt generation
Attention indicator blink interrupt enable. When set and PEX_PME_MES_DR[AIB]=1 generates an
interrupt.
1 Enable attention indicator blink message interrupt generation
0 Disable attention indicator blink message interrupt generation
ENL23
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
18
IE
EXL23
Table 17-11. PEX_PME_MES_IER Field Descriptions
19
IE
20
—
HRD
21
IE
LDD
IE
22
All zeros
All zeros
23
—
—
Description
24
AION
IE
25
AIB
26
IE
AIOF
27
IE
PCI Express Interface Controller
PION
28
IE
Access: Read/Write
PIB
IE
29
PIOF
30
IE
ABP
17-17
15
31
IE