MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 314

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8.4.1.21
The DDR Write Leveling Control register, shown in
it is supported for DDR3 memory devices.
8-40
Offset 0x174
Reset
12–15
16–19
20–23
24–31
Bits
W
R
WRLVL_EN
0
ZQOPER
Name
ZQCS
DDR Write Leveling Control (DDR_WRLVL_CNTL)
—
—
1
Figure 8-22. DDR Write Leveling Control Register (DDR_WRLVL_CNTL)
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
4 5
Table 8-26. DDR_ZQ_CNTL Field Descriptions (continued)
WRLVL_
Normal Operation Full Calibration Time (t
allowed for DRAM ZQ calibration when exiting self refresh. Each chip select is calibrated
separately, and this time must elapse after the ZQCL command is issued for each chip select
before a separate command may be issued.
0000-0110 Reserved
0111 128 clocks
1000 256 clocks
1001 512 clocks
1010 1024 clocks
1011-1111 Reserved
Reserved, should be cleared.
Normal Operation Short Calibration Time (t
be allowed for DRAM ZQ calibration during dynamic calibration which is issued every 32 refresh
cycles. Each chip select is calibrated separately, and this time must elapse after the ZQCS
command is issued for each chip select before a separate command may be issued.
0000 1 clocks
0001 2 clocks
0010 4 clocks
0011 8 clocks
0100 16 clocks
0101 32 clocks
0110 64 clocks
0111 128 clocks
1000 256 clocks
1001 512 clocks
1010-1111 Reserved
Reserved, should be cleared.
MRD
7
— WRLVL_ODTEN —
8
9
11
12 13
All zeros
Figure
WRLVL_
DQSEN
ZQoper
Description
8-22, provides controls for write leveling, as
ZQCS
15 16
WRLVL_
). Determines the number of cycles that must be
). Determines the number of cycles that must
SMPL
19 20
—
WRLVL_WLR
21
23
Freescale Semiconductor
24
Access: Read/Write
—
26 27 28
WRLVL_
START
31