MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 706

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
The 24-bit ECC code word format is shown in
LBCR[EPAR] = 1 changes ECC polarity, and thus omits negation of each P
The placement of ECC code words in relation to FMR[ECCM] is shown in
devices, only a single 512-byte main region is ECC-protected. For large-page devices, there are four
adjacent main regions, and each has a 16-byte spare region—of which only one is shown in the figure. If
eLBC is configured to generate ECC (BRn[DECC] = 10), FCM will substitute on full-page write transfers
the three code word bytes in place of the spare region data originally provided at the locations shown in
Figure 13-52
reference. Transfers shorter than a full page, however, require software to prepare the appropriate ECC in
the spare region. Similarly, FCM can check and correct bit errors on full-page reads if BRn[DECC] = 01
or 10. A correctable error is a single bit error in any 512-byte block of main region data, as judged by
comparison of a regenerated ECC with the ECC retrieved from the spare region, or a single bit error in the
retrieved ECC only. Bit errors in the main region are corrected before FCM completes its final read transfer
and signals an event in LTESR[CC]. The bit vector in LTECCR[SBCE] can be checked on FCM CC event
to find out if any 512-byte block or the corresponding ECC have single bit correctable errors. Errors that
appear more complex (two or more bits in error per 512-byte block) are not corrected, but are flagged as
parity errors by FCM. The bit vector in LTEATR[PB] or LTECCR[MBUE] can be checked to determine
which 512-byte blocks in a large-page NAND Flash main region were found to be uncorrectable.
13-64
block
ECC
and write the same 24-bit ECC code in the appropriate FECCn register for software
Figure 13-51. ECC Layout for LBCR[EPAR] = 0 (~ represents logical negation)
column
byte 510
byte 511
parity
byte 0
byte 1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
EC0
EC1 ~P
EC2
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
P
0 (MSB)
~P
1
~P
P
1024
2
64
P
4
1
’
P
4
P
~P
~P
1
~P
P
Figure 13-50. FCM ECC Calculation
1024
1
2
64
’
P
4
’
1
’
’
’
P
1
~P
~P
P
~P
2
2
512
P
32
2
1
’
P
4
Figure 13-51
’
P
1
~P
P
~P
~P
2
P
’
3
512
32
2
1
’
’
’
’
~P
~P
P
P
P
~P
P
P
P
P
P
1
2
4
4
8
256
8
8
16
’ = bit6
’ = bit5
’ = bit3
8
8
’ = bit7
1
’
’
for normal ECC polarity. Setting
P
P
row parity
16
16
~P
~P
~P
’
5
256
16
1
bit 4
bit 4
bit 2
....
’
’
’
~P
~P
bit 0
~P
P
P
6
2048
2048
2048
bit 2
bit 1
bit 1
128
Figure
N
8
and P
’
P
~P
~P
7 (LSB)
8
~P
bit 0
bit 0
bit 0
’(prev)
13-52. For small-page
2048
128
N
8
Freescale Semiconductor
’ bit.
’
’
’
P
P
P
1
2
4
’(prev)
’(prev)
’(prev)