MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1619

BOARD DEV SYSTEM MPC8536E

MPC8536DS

Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets

Specifications of MPC8536DS

Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Freescale Semiconductor
0x07C–
0x0A4–
0x0C8–
0x0D8–
0x0F8–
0x094–
0x0CC
0x0DC
Offset
0x08C
0x09C
0x0AC
0x0BC
0x0C0
0x0C4
0x0D0
0x0D4
0x0EC
0x0FC
0x0A0
0x0B0
0x0B4
0x0B8
0x0E0
0x0E4
0x0E8
0x0F0
0x0F4
0x070
0x074
0x078
0x080
0x084
0x088
0x090
MAMR—UPMA mode register
MBMR—UPMB mode register
MCMR—UPMC mode register
Reserved
MRTPR—Memory refresh timer prescaler register
MDR—UPM/FCM data register
Reserved
LSOR—Special operation initiation register
Reserved
LURT—UPM refresh timer
Reserved
LTESR—Transfer error status register
LTEDR—Transfer error disable register
LTEIR—Transfer error interrupt register
LTEATR—Transfer error attributes register
LTEAR—Transfer error address register
LTECCR—Transfer error ECC register
Reserved
LBCR—Configuration register
LCRR—Clock ratio register
Reserved
FMR—Flash mode register
FIR—Flash instruction register
FCR—Flash command register
FBAR—Flash block address register
FPAR—Flash page address register
FBCR—Flash byte count register
Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table A-7. Enhanced Local Bus Controller Registers (continued)
Enhanced Local Bus Controller—Block Base Address 0x0_5000
Register
Complete List of Configuration, Control, and Status Registers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
w1c
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x8000_000 n
0x0000_0 n 00
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
13.3.1.10/13-28
13.3.1.11/13-29
13.3.1.12/13-30
13.3.1.13/13-31
13.3.1.14/13-31
13.3.1.15/13-32
13.3.1.16/13-34
13.3.1.17/13-35
13.3.1.18/13-37
13.3.1.19/13-38
13.3.1.20/13-39
13.3.1.21/13-39
13.3.1.22/13-41
13.3.1.4/13-21
13.3.1.4/13-21
13.3.1.4/13-21
13.3.1.5/13-23
13.3.1.6/13-23
13.3.1.7/13-24
13.3.1.4/13-21
13.3.1.9/13-26
Section/Page
A-7

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