MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1294

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
20-20
RSTD
RSTC
RSTA
Field
INITA
0–3
4
5
6
7
Reserved
Initialization active. When this bit is written ‘1’, 80 SD clocks are sent to the card. After the 80 clocks are sent,
this bit is self-cleared. This bit is very useful during the card power-up period when 74 SD clocks are needed and
clock auto-gating feature is enabled.
Writing one to this bit when it is already set has no effect. Clearing this bit at any time does not affect it. When
PRSSTAT[CIHB] or PRSSTAT[CDIHB] is set, writing a one to this bit is ignored. That is, when the command line
or data line is active, writing to this bit is not allowed.
Software reset for SDHC_DAT line. The DMA and part of the data circuit are reset. The following registers and
bits are cleared by this bit:
0 Work
1 Reset
Software reset for SDHC_CMD line. Only part of the command circuit is reset. The following registers and bits
are cleared by this bit:
0 Work
1 Reset
Software reset for all. This reset affects the entire host controller except for the card-detection circuit. Register
bits of type ROC, RW, RW1C, and RWAC are cleared.
During its initialization, the host driver should set this bit to reset the eSDHC. The eSDHC should clear this bit
when capabilities registers are valid and the host driver can read them. Additional use of the this bit does not
affect the value of the capabilities registers. After this bit is set, it is recommended the host driver reset the
external card and re-initialize it.
0 Work
1 Reset
• DATPORT register
• Buffer is cleared and initialized; PRSSTAT register
• PRSSTAT[BREN, BWEN, RTA, WTA, DLA, CDIHB]
• PROCTL[CREQ, SABGREQ]
• IRQSTAT[BRR, BWR, DINT, BGE, TC]
• DSADDR
• BLKATTR
• PROCTL[IABG, RWCTL, DTW]
• IRQSTAT[DMAE, DEBE, DCE, DTOE]
• IRQSTATEN[DMASEN, DEBESEN, DCESEN, DTOESEN, BRRSEN, BWRSEN, DINTSEN, BGESEN,
• IRQSIGEN[DMAEIEN, DEBEIEN, DCEIEN, DTOEIEN, BRRIEN, BWRIEN, DINTIEN, BGEIEN, TCIEN]
• WML
• PRSSTAT[CIHB]
• IRQSTAT[CC]
• CMDARG
• XFERTYP
• CMDRSP0
• CMDRSP1
• CMDRSP2
• CMDRSP3
• PRSSTAT[CDIHB, CIHB]
• IRQSTAT[AC12E, CIE, CEBE, CCE, CTOE]
• IRQSTATEN[AC12ESEN, CIESEN, CEBESEN, CCESEN, CTOESEN, CCSEN]
• IRQSIGEN[AC12EIEN, CIEIEN, CEBEIEN, CCEIEN, CTOEIEN, CCIEN]
• AUTOC12ERR
TCSEN]
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 20-13. SYSCTL Field Descriptions
Description
Freescale Semiconductor