MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 464

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
While one channel owns a particular EU, it is possible for two or more other channels to request access to
the same EU; in this case, an arbitration scheme determines which channel is granted next access. EU
arbitration schemes are similar to channel arbitration mentioned above, and are described in
Section 10.5.2, “Arbitration
If a channel needs two EUs, a primary and a secondary, it requests them one at a time. Sometimes a channel
reserves one EU and then has to wait for some other channel(s) to finish before obtaining the second
requested EU. Though such waiting may occur, the requests are always eventually satisfied. Deadlock is
avoided through the following design rules:
10.4.1.3
When a channel completes operation on a descriptor, it can notify the host that it is done through interrupt
and/or through a writeback of the descriptor header dword. In case the descriptor operation is not
completed or completed with a known error, the host may be notified by an error interrupt. The error
interrupts, done interrupts and header writeback are described as follows:
10.4.2
Active channels can assert done and error interrupts to the controller. As with all SEC interrupt events,
channel done and error interrupts are reflected in the controller’s interrupt status register. Channel do not
10-34
1. The channel always requests the secondary EU first.
2. In cases where both a primary and secondary are used, the choices for primaries and secondaries
•
•
•
are distinct sets. Primaries are AESU, AFEU, DES, and KFEU, and the secondaries are MDEU and
CRCU.
Error interrupts are always enabled at the channel level, but can be masked at the controller level.
For more details concerning these interrupts, see
Done interrupts are enabled on a per-channel basis by programming the channel’s configuration
register. For programming details, refer to
Section 10.4.4.1, “Channel Configuration Register
Independently of the done interrupt, channels can inform software of their completion status via
header writebacks. Like done interrupts, writebacks are enabled on a per-channel basis by
programming the CCR. If enabled, then upon completion the channel writes 0xFF to the DONE
byte in the original descriptor header (see
a specific descriptor. The CCR can also be programmed so that the channel writes back a status
code indicating whether an integrity checking EU has encountered a mismatch between the
received ICV and the recalculated ICV.
that are updated in this case.
For more details on programming the CCR for writeback, see
Configuration Register
Channel Interrupts
Channel Host Notification
The done and status writebacks are not performed should the channel signal
any error during processing. For example, there are no writebacks in case of
a failing, unmasked ICV check in an EU.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Algorithms.”
(CCR).”
Table 10-5
Table
NOTE
Section 10.4.2.1, “Channel Done
10-5), allowing software to poll for completion of
Section 10.4.2.2, “Channel Error
shows the specific bytes in the descriptor header
(CCR).”
Section 10.4.4.1, “Channel
Interrupt,” and
Freescale Semiconductor
Interrupt.”