MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1510

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
23-18
Bits
10
11
12
13
14
15
16
17
18
19
20
21
22
23
9
eSDHC
SRDS2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
SATA1
SATA2
Name
USB2
USB3
E500
DDR
DMA
SPI
TB
L2
—
—
—
Table 23-13. DEVDISR Field Descriptions (continued)
USB 2 controller disable.
0 USB 2 enable
1 USB 2 disable
USB 3 controller disable.
0 USB 3 enable
1 USB 3 disable
L2 controller disable.
0 L2 enable
1 L2 disable
eSDHC controller disable.
0 eSDHC enable
1 eSDHC disable
SATA 1 controller disable.
0 SATA 1 enable
1 SATA 1 disable
Reserved
SPI controller disable.
0 SPI enable
1 SPI disable
DDR SDRAM controller disable.
0 DDR controller enable
1 DDR controller disable
e500 core disable.
0 e500 core enable
1 e500 core disable. Places the core in the core_stopped state in which it does not
Time base (timer facilities) of the e500 core disable.
0 Timer facilities enabled
1 Timer facilities disabled.
Reserved
SATA 2 controller disable.
0 SATA 2 enable
1 SATA 2 disable
DMA controller disabled.
0 DMA controller enabled
1 DMA controller disabled
Reserved
SerDes 2 disabled.
0 SerDes 2 enabled
1 SerDes 2 disabled
respond to interrupts. Equivalent to nap mode. Instruction fetching is stopped,
snooping is disabled, and clocks are shut down to all functional units of the core
including the timer facilities.
Description
Freescale Semiconductor