MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 731

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

typically set before the line that contains UTA = 1. Note that if WAEN and NA are both set in the same
RAM word, NA causes the burst address to increment once as normal regardless of whether the UPM
freezes.
13.4.4.5
If LUPWAIT is to be considered an asynchronous signal, which can be asserted/negated at any time, no
UPM RAM word must contain both WAEN = 1 and UTA = 1 simultaneously.
However, programming WAEN = 1 and UTA = 1 in the same RAM word, under certain conditions, allows
the UPM to treat LUPWAIT as a synchronous signal, which must meet set-up and hold times in relation
to the rising edge of the bus clock. The conditions are as follows:
In this mode, as soon as UPM samples LUPWAIT negated on the rising edge of the bus clock, it
immediately generates an internal transfer acknowledge, which allows a data transfer one bus clock cycle
later. The generation of transfer acknowledge is early because LUPWAIT is not re-synchronized. The
acknowledge occurs early or normally depending on whether the UPM was already frozen inWAIT cycles
Freescale Semiconductor
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The PLL must be enabled, that is, LCRR[PBYP] = 0.
DLT3 bit must be cleared in the same RAM word to avoid mid-sampling of read data.
LBCR[LPBSE] = 0 and MXMR[GPL4] = 1
The combination WAEN=1 and UTA=1 should be in the RAM word next to the word which gets
frozen by LUPWAIT assertion. This condition limits the use of this mode to cases where the exact
cycle of LUPWAIT assertion is predictable.
Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge
LUPWAIT
LGPL1
WAEN
LCS n
LCLK
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
T1
T2
T3
T4
TA
c1 c2 c3 c4 c5 c6 c7 c8
Word n
A
Figure 13-70. Effect of LUPWAIT Signal
Word n+1
B
c9 c10 c11
Word n+2
C
c12
Wait
Enhanced Local Bus Controller
Word n+3
c13 c14
D
13-89