MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1507

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 23-12
Freescale Semiconductor
Offset 0x060
Reset
Reset
Bits
0
1
2
3
4
5
W
W
R
R
PCI_REQGNT3 Enables PCI_REQ[3] and PCI_GNT[3] signals
PCI_REQGNT4 Enables PCI_REQ[4] and PCI_GNT[4] signals
SD_DATA SDHC_CD SDHC_WP PCI_REQGNT3 PCI_REQGNT4 USB1 USB2
SDHC_WP
SDHC_CD
SD_DATA
16
0
Name
USB1
describes the bit settings of PMUXCR.
Figure 23-9. Alternate Function Pin Multiplex Control Register (PMUXCR)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
1
Enables SD_DATA[4:7] signals
0 SD_DATA[4:7] is not exposed to pins; the pins retain the primary function as SPI.
1 SD_DATA[4:7] is exposed to pins as follows:
Enables SDHC_CD signals
0 SDHC_CD is not exposed to pins; the pins retain the primary function as GPIO.
1 SDHC_CD is exposed to pins as follows:
Enables SDHC_WP signals
0 SDHC_WP is not exposed to pins; the pins retain the primary function as GPIO.
1 SDHC_WP is exposed to pins as follows:
Note: If PMUXCR[SDHC_WP]=0 and eSDHC write functionality is required, then
0 PCI_REQ[3] and PCI_GNT[3] are not exposed to pins; the pins retain the primary function as GPIO.
1 PCI_REQ[3] and PCI_GNT[3] are exposed to pins as follows:
0 PCI_REQ[4] and PCI_GNT[4] are not exposed to pins; the pins retain the primary function as GPIO.
1 PCI_REQ[4] and PCI_GNT[4] are exposed to pins as follows:
Enables USB1_PCTL0 and USB1_PCTL1 signals
0 USB1_PCTL0 and USB1_PCTL1 are not exposed to pins; the pins retain the primary function as
1 USB1_PCTL0 and USB1_PCTL1 are exposed to pins as follows:
GENCFGR[SDHC_WP_INV] should be set to 1.
GPIO.
SPI_CS[0] functions as SDHC_DAT[4]
SPI_CS[1] functions as SDHC_DAT[5]
SPI_CS[2] functions as SDHC_DAT[6]
SPI_CS[3] functions as SDHC_DAT[7]
GPIO[4] functions as SDHC_CD
GPIO[5] functions as SDHC_WP
GPIO[0] functions as PCI_REQ[3]
GPIO[2] functions as PCI_GNT[3]
GPIO[1] functions as PCI_REQ[4]
GPIO[3] functions as PCI_GNT[4]
GPIO[6] functions as USB1_PCTL0
GPIO[7] functions as USB1_PCTL1
2
Table 23-12. PMUXCR Field Descriptions
3
—
All zeros
All zeros
4
Description
5
6
7
—
Access: Read/Write
13
29
DMA0 DMA2
DMA1 DMA3
Global Utilities
14
30
23-15
15
31