MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1586

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug Features and Watchpoint Facility
25.1.3.1
The LBC and the DDR SDRAM controller can drive debug information (source ID and data-valid
indicator) onto MSRCID[0:4] and MDVAL. As shown in
controls multiplexing. If MSRCID0 is low when sampled during POR, the local bus SDRAM information
appears on MSRCID[0:4] and MDVAL; otherwise, the DDR SDRAM debug information is presented.
25.1.3.2
MSRCID1 is sampled during POR to multiplex either ECC or debug information on the ECC pins of the
DDR SDRAM interface. As shown in
in debug mode and provide memory debug source ID and data-valid information. MSRCID1 must be
pulled low during POR to use the ECC pins in debug mode. If MSRCID1 is unconnected, an internal
pull-up resistor ensures the ECC pins always source DDR SDRAM error correcting code information as
their default power-on reset configuration.
25.1.3.3
The watchpoint monitor supports the following operating modes:
25.1.3.4
The trace buffer supports the following operating modes:
25-4
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Immediate trigger arming (one-level triggering)—The watchpoint monitor triggers as soon as the
first trigger event occurs.
Wait for trigger arming (two-level triggering)—The watchpoint monitor waits for a specific event
before enabling (arming) the trigger logic. The monitor does not respond to trigger events until
after the arming event occurs. This function is similar to two-level triggering on a logic analyzer.
Assert TRIG_OUT on hit—The debug block can be programmed to assert the TRIG_OUT signal
when a programmed watchpoint monitor event occurs. This signal can be used to trigger a logic
analyzer.
Immediate trigger arming (one-level triggering)—The trace buffer triggers as soon as the first
trigger event occurs.
Wait for trigger arming (two-level triggering)—The trace buffer waits for a specific event before
enabling (arming) the trigger logic. The trace buffer does not respond to trigger events until after
the arming event occurs. This function is similar to two-level triggering on a logic analyzer.
Specific interface selection—The trace buffer can be programmed to trace one of several internal
interfaces.
Local Bus (LBC) Debug Mode
DDR SDRAM Interface Debug Modes
Watchpoint Monitor Modes
Trace Buffer Modes
If the DDR ECC pins are in debug mode (configured for debug during
POR), ECC checking is disabled in the memory controller. In this case,
MECC[0:4] do not provide ECC information and must not be connected to
SDRAM devices.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table
25-1, if MSRCID1 is low during POR, the ECC pins operate
NOTE
Table
25-1, the MSRCID0 value during POR
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