MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 943

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.6.7.2
The 1588 timer module can be partitioned into four different sub-modules as shown in
14.6.7.3
Every incoming packet’s 8-byte time stamp is inserted into the packet data buffer as padding alignment
bytes. Time-stamp insertion into the data buffer requires RCTRL[PAL] to be set to a value greater than or
equal to 8 and the control bit RCTRL[TS] bit to be set.
14.6.7.3.1
The required timestamp point, as specified in the IEEE 1588 Specification Sep-2004 (IEC 61588 First
Edition), is shown in Figure 14-150. From this, it is clear that the end of the SFD is the critical point in the
MII data stream.
The sample point coincides with the cycle after the SFD (Start of Frame Delimiter) detection by the MAC.
For received frames, this will be at least 4 bit times (MII) or 8 bit times (GMII) after the message
timestamp point specified in [1588]. For transmission, the eTSEC sample point precedes the sample point
Freescale Semiconductor
0
Timer Logic Overview
Time-Stamp Insertion on the Received Packets
Preamble
Timestamp Point
Octet
1
1588 Timer
TMRCK
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Clock
0
1
Figure 14-150. Ethernet Sampling Points for 1588
0
Figure 14-149. 1588 Timer Design Partition
1
TMRMAC
0
Message Timestamp
1
Start of Frame
SFD Detection
Delimiter
Ethernet
TMRREG
0
Rx & Tx
Point
Register Array
Time Stamp
1
Bit Time
0
1
1
1
SEL
Rx Pins
0
Enhanced Three-Speed Ethernet Controllers
0
Ethernet MAC
Start of Frame
First Octet
Following
0
eTSEC
0
Tx Pins
0
Figure
0
0
14-149.
14-195