MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 249

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.6.2
Memory-mapped SRAM coherency rules are as follows:
6.7
The caches can be locked and cleared using the following methods:
6.7.1
The entire L2 cache can be locked by setting L2CTL[L2DO] = 1 and L2CTL[L2IO] = 1. This has the
effect of preventing any further allocation of new lines in the cache by core requests. If there are lines in
the cache that are not valid, they cannot be used by core requests until the cache is unlocked. While the
cache is locked, read requests are serviced as normal, and snooping continues as normal to maintain
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The L2 cache supports burst writes that allocate and/or lock an L2 cache line from peripheral
devices or I/O controllers through a write allocate transaction. See the system logic programming
model (for example, that of the DMA controller) for details on how to set the transaction type for
cache external writes to the L2.
External (non–core-initiated) accesses to memory-mapped SRAM must be marked
coherency-required. External accesses to memory-mapped SRAM marked coherency-not-required
may cause an address unavailable error.
Accesses to memory-mapped SRAM are cacheable only in the corresponding e500 L1 caches.
External accesses must be marked cache-inhibited or be performed with non-caching transactions.
Cache locking methods
— Individual line locks are set and cleared using instructions defined by the e500 cache locking
— A lock attribute can be attached to write operations.
— Individual line locks are set and cleared through core-initiated instructions, by external reads
— The entire cache can be locked by setting a configuration registers appropriately
Methods for clearing locks
— Individual locks can be cleared by cache locking APU instructions (Instruction Cache Block
— Flash clearing of all instruction and/or data locks can be done by writes to configuration
— An unlock attribute can be attached to I/O read operations.
L2 Cache Locking
APU, which is part of the Freescale embedded implementation standards (EIS). These
instructions include Data Cache Block Touch and Lock Set (dcbtls), Data Cache Block Touch
for Store and Lock Set (dcbtstls), and Instruction Cache Block Touch and Lock Set (icbtls).
For detailed information about these instructions, see the PowerPC e500 Core Reference
Manual.
or writes, or by accesses to programmed memory ranges defined in L2 cache external write
address registers (L2CEWARn).
Lock Clear (icblc) and Data Cache Block Lock Clear (dcblc)) or by snooped flush unless the
entire cache is locked.
registers.
Memory-Mapped SRAM Coherency Rules
Locking the Entire L2 Cache
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
L2 Look-Aside Cache/SRAM
6-29