MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 615

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The I
must be set before allowing the I
I2CCR[TXAK] needs to be cleared again for subsequent I
setting up the I2CCR for the next transfer.
11.5.5
At the end of a data transfer, if the master still wants to communicate on the bus, it can generate another
START condition followed by another slave address without first generating a STOP condition. This is
accomplished by setting I2CCR[RSTA].
11.5.6
It is sometimes necessary to force the I
(even though SDA may already be driven, which indicates that the bus is busy). This can occur when a
system reset does not cause all I
while this I
used to force this I
11.5.7
In the slave interrupt service routine, the module addressed as a slave should be tested to check if a calling
of its own address has been received. If I2CSR[MAAS] is set, software should set the transmit/receive
mode select bit (I2CCR[MTX]) according to the R/W command bit (I2CSR[SRW]). Writing to I2CCR
clears MAAS automatically. MAAS is read as set only in the interrupt handler at the end of that address
cycle where an address match occurred; interrupts resulting from subsequent data transfers clear MAAS.
A data transfer can then be initiated by writing to I2CDR for slave transmits or dummy reading from
I2CDR in slave-receive mode. The slave drives SCL low between byte transfers. SCL is released when the
I2CDR is accessed in the required mode.
11.5.7.1
In the slave transmitter routine, the received acknowledge bit (I2CSR[RXAK]) must be tested before
sending the next byte of data. The master signals an end-of-data by not acknowledging the data transfer
from the slave. When no acknowledge is received (I2CSR[RXAK] is set), the slave transmitter interrupt
routine must clear I2CCR[MTX] to switch the slave from transmitter to receiver mode. A dummy read of
I2CDR then releases SCL so that the master can generate a STOP condition. See
Service Routine Flowchart.”
Freescale Semiconductor
1. Disable the I
2. Enable the I
3. Read the I2CDR
4. Return the I
2
C controller automatically generates a STOP if I2CCR[TXAK] is set. Therefore, I2CCR[TXAK]
2
Generation of Repeated START
Generation of SCL When SDA Low
Slave Mode Interrupt Service Routine
C module is coming out of reset and stays low indefinitely. The following procedure can be
Slave Transmitter and Received Acknowledge
2
2
C module to generate SCL so that the device driving SDA can finish its transaction:
2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
C module to slave mode by setting I2CCR to 0x80
C module by setting I2CCR to 0xA0
C module and set the master bit by setting I2CCR to 0x20
2
C devices to be reset. Thus, SDA can be driven low by another I
2
C module to receive the last data byte on the I
2
C module to become the I
2
C transactions. This can be accomplished when
2
C bus master out of reset and drive SCL
Section 11.5.8, “Interrupt
2
C bus. Eventually,
I
2
2
C Interfaces
C device
11-23