MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1524

BOARD DEV SYSTEM MPC8536E

MPC8536DS

Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets

Specifications of MPC8536DS

Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Global Utilities
23.4.1.24 DDR Clock Disable Register (DDRCLKDR)
Shown in
SDRAM controller.
Table 23-27
23-32
0–25
Bits
Offset 0xB28
Reset
Reset
26
27
28
29
30
31
W
W
R
R
Figure
16
0
describes the bit settings of DDRCLKDR.
MCK0_DIS
MCK1_DIS
MCK2_DIS
MCK3_DIS
MCK4_DIS
MCK5_DIS
23-24, the DDRCLKDR contains bits that allow disabling the clocks of the DDR
Name
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 23-24. DDR Clock Disable Register (DDRCLKDR)
Reserved
DDR clock 0 disable
0 MCK0 is enabled.
1 MCK0 is disabled.
DDR clock 1 disable
0 MCK1 is enabled.
1 MCK1 is disabled.
DDR clock 2 disable
0 MCK2 is enabled.
1 MCK2 is disabled.
DDR clock 3 disable
0 MCK3 is enabled.
1 MCK3 is disabled.
DDR clock 4 disable
0 MCK4 is enabled.
1 MCK4 is disabled.
DDR clock 5 disable
0 MCK5 is enabled.
1 MCK5 is disabled.
Table 23-27. DDRCLKDR Field Descriptions
All zeros
All zeros
25
MCK0_
DIS
26
Description
MCK1_
DIS
27
MCK2_
DIS
28
MCK3_
DIS
29
Freescale Semiconductor
MCK4_
DIS
30
MCK5_
DIS
15
31

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