MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 668

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0x0_50B0
Enhanced Local Bus Controller
Table 13-15
13.3.1.9
The transfer error status register (LTESR) indicates the cause of an error or event. LTESR, shown in
Figure
can clear but not set bits. A bit is cleared whenever the register is written, and the data in the corresponding
bit location is a 1. For example, to clear only the write protect error bit (LTESR[WP]) without affecting
other LTESR bits, 0x0400_0000 should be written to the register. After any error/event reported by
LTESR, LTEATR[V] must be cleared for LTESR to updated again.
Reset
Reset
13-26
8–31
Bits
0–7
W
W
R
R
BM
13-13, is a write-1-to-clear register. Reading LTESR occurs normally; however, write operations
16
0
Name
LURT UPM refresh timer period. Determines, along with the timer prescaler (MRTPR), the timer period according
—
FCT
describes LURT fields.
Transfer Error Status Register (LTESR)
1
to the following equation:
Example: For a 266-MHz system clock and a required service rate of 15.6 µs, given MRTPR[PTP] = 32, the
LURT value should be 128 decimal. 128/(266 MHz/32) = 15.4 µs, which is less than the required service
period of 15.6 µs.
Note that the reset value (0x00) sets the maximum period to 256 x MRTPR[PTP] system clock cycles.
Reserved
PAR
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
3
Figure 13-13. Transfer Error Status Register (LTESR)
—
4
Table 13-15. LURT Field Descriptions
WP
5
6
TimerPeriod
—
—
7
All zeros
All zeros
ATMW ATMR
Description
8
=
--------------------------------------------- -
⎛
⎝
Fsystemclock
--------------------------------------- -
MRTPR PTP
9
LURT
10
—
11
⎞
⎠
CS
12
Freescale Semiconductor
13
29
UCC
—
30
Access: w1c
CC
15
31