MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1404

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.6.8
The structure of an iTD is presented in Isochronous (High-Speed) Transfer Descriptor (iTD). There are
four distinct sections to an iTD:
21.6.8.1
The host controller uses FRINDEX register bits 12–3 to index into the periodic frame list. This means that
the host controller visits each frame list element eight consecutive times before incrementing to the next
periodic frame list element. Each iTD contains eight transaction descriptions, which map directly to
FRINDEX register bits 2–0. Each iTD can span 8 micro-frames worth of transactions. When the host
controller fetches an iTD, it uses FRINDEX register bits 2–0 to index into the transaction description array.
When the first iTD in the periodic list is traversed after periodic schedule is enabled, the value of
FRINDEX[2:0] may be other then 0, so the first transaction issued by the controller may be any of the eight
available active transactions. If the active bit in the Status field of the indexed transaction description is
cleared, the host controller ignores the iTD and follows the Next pointer to the next schedule data structure.
21-70
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The first field is the Next Link Pointer. This field is for schedule linkage purposes only.
Transaction description array. This area is an eight-element array. Each element represents control
and status information for one micro-frame's worth of transactions for a single high-speed
isochronous endpoint.
The buffer page pointer array is a 7-element array of physical memory pointers to data buffers.
These are 4K aligned pointers to physical memory.
Endpoint capabilities. This area utilizes the unused low-order 12 bits of the buffer page pointer
array. The fields in this area are used across all transactions executed for this iTD, including
endpoint addressing, transfer direction, maximum packet size and high-bandwidth multiplier.
1024, 512, or 256
Managing Isochronous Transfers Using iTDs
Host Controller Operational Model for iTDs
Elements
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Periodic Frame List
Figure 21-46. Example Periodic Schedule
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Poll Rate: 1
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A
A
A
A
A
A
Poll Rate: N –– > 1
8
Isochronous Transfer
Descriptor(s)
A
4
• • •
1
Last
Periodic has
End of
List Mark
Interrupt Queue
Heads
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