MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1296

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
20.4.10 Interrupt Status Register (IRQSTAT)
An interrupt is generated when one of the status bits and its corresponding interrupt enable bit are set. For
all bits, writing one to a bit clears it, while writing zero keeps the bit unchanged. More than one status can
be cleared with a single register write. For a card interrupt (IRQSTAT[CINT]), the card must stop asserting
the interrupt before writing one to clear. Otherwise, the CINT bit is set again.
20-22
HCKEN
PEREN
IPGEN
Field
29
30
31
Peripheral clock enable. If set, the peripheral clock is always active and no automatic gating is applied, thus
SDHC_CLK is active only except auto gating-off during buffer danger. If cleared, the peripheral clock is
automatically off when no transaction is on the SD bus. Clearing this bit does not stop SDHC_CLK immediately.
The peripheral clock will be internally gated off, if none of the following factors are met:
0 The peripheral clock is internally gated off
1 The peripheral clock is not automatically gated off
Master clock enable. If set, master clock is always active and no automatic gating is applied. If cleared, master
clock is automatically off when no data transfer is on SD bus.
Note: Master clock is the clock to the DMA engine and to the system bus interface logic.
0) Master clock is internally gated off
1) Master clock is not automatically gated off
Controller clock enable. If this bit is set, the controller clock is always active and no automatic gating is applied.
The controller clock is internally gated off, if neither the following factors is met:
Note: The controller clock is not auto-gated off if the peripheral clock is not gated off. So, clearing this bit only
0 The controller clock is internally gated off
1 The controller clock is not automatically gated off
• Command part is reset
• Data part is reset
• Soft reset
• Command is about to send
• Clock divisor is just updated
• Continue request is just set
• This bit is set
• Card insertion is detected
• Card removal is detected
• Card external interrupt is detected
• 80 clocks for initialization phase is ongoing
• Command part is reset
• Data part is reset
• Soft reset
• Command is about to send
• Clock divisor is just updated
• Continue request is just set
• This bit is set
• Card insertion is detected
• Card removal is detected
• Card external interrupt is detected
• The controller clock is not gated off
does not take effect if SYSCTL[PEREN] is not cleared.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 20-13. SYSCTL Field Descriptions (continued)
Description
Freescale Semiconductor