MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 395

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.2.3
The GTBCRs contain the base counts for each of the four PIC timers in each of the two groups, as shown
in
zero. Note that when zero is written to the base count field, (and GTCCRxn[CI] = 0), the timer generates
an interrupt on every timer cycle.
Table 9-15
9.3.2.4
The GTVPRs contain the interrupt vector and the interrupt priority values for the timers as shown in
Figure
Interrupt Control,”
Freescale Semiconductor
Offset Group A: GTVPRA0: 0x1120; GTVPRA1: 0x1160; GTVPRA2: 0x11A0; GTVPRA3: 0x11E0;
1–31 BASE CNT Base count. When CI transitions from 1 to 0, this value is copied into the corresponding GTCCR xn and the
Reset
Bits
Offset Group A: GTBCRA0: 0x1110; GTBCRA1: 0x1150; GTBCRA2: 0x1190; GTBCRA3: 0x11D0
Reset 1
0
Figure
W
R
W
R
Group B: GTVPRB0: 0x2120; GTVPRB1: 0x2160; GTVPRB2: 0x21A0; GTVPRB3: 0x21E0
MSK
9-14. They also contain the mask and activity fields for all the timers. See
Group B: GTBCRB0: 0x2110; GTBCRB1: 0x2150; GTBCRB2: 0x2190; GTBCRB3: 0x21D0
Name
1
CI
0
0
CI
9-13. This value is reloaded into the corresponding GTCCRxn when the current count reaches
1
0
describes the GTBCRxn fields.
A
0
1
Global Timer Base Count Registers (GTBCRA0–GTBCRA3,
GTBCRB0–GTBCRB3)
Global Timer Vector/Priority Registers (GTVPRA0–GTVPRA3,
GTVPRB0–GTVPRB3)
0
0
2
Count inhibit. Always set following reset
0 Counting enabled
1 Counting inhibited
toggle bit is cleared. If CI is already cleared (counting is in progress), the base count is copied to the
GTCCR xn at the next zero crossing of the current count.
0
0
for information on IPR and ISR.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
0
Figure 9-14. Global Timer Vector/Priority Register (GTVPR xn )
0
Figure 9-13. Global Timer Base Count Register (GTBCR xn )
0
0
0
—
0
0
0
Table 9-15. GTBCR xn Field Descriptions
0
0
0
0
0
0
11 12
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PRIORITY
0
0
BASE CNT
0
15 16
Description
0
0
0
0
0
0
Programmable Interrupt Controller (PIC)
0
VECTOR
0
0
Section 9.4.1, “Flow of
0
0
0
0
Read/Write
0
0
Access:
Access:
0
0
Mixed
9-25
31
0
31
0