MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 825

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Bits
26
27
28
29
30
31
PAD/CRC
CRC EN
Length
Duplex
Frame
MPEN
Name
check
Huge
Full
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Huge frame enable. This bit is cleared by default.
0 Limit the length of frames received to less than or equal to the maximum frame length value
1 Frames are transmitted and received regardless of their relationship to the maximum frame length.
Note that if Huge Frame is cleared, the user must ensure that adequate buffer space is allocated for
Length check. This bit is cleared by default.
0 No length field checking is performed.
1 The MAC checks the frame’s length field on receive to ensure it matches the actual data field length.
Magic packet enable for Ethernet modes. This bit is cleared by default. MPEN should be enabled only
after GRACEFUL RECEIVE STOP and GRACEFUL TRANSMIT STOP are completed successfully (in
other words, transmission and reception have stopped).
0 Normal receive behavior on receive, or Magic Packet mode has exited with reception of a valid
1 Commence Magic Packet detection by the MAC provided that frame reception is enabled in
Pad and append CRC. This bit is cleared by default.This bit must be set when in half-duplex mode
(MACCFG2[Full Duplex] is cleared).
0 Frames presented to the MAC have a valid length and contain a CRC.
1 The MAC pads all transmitted short frames and appends a CRC to every frame regardless of
CRC enable. If the configuration bit PAD/CRC ENABLE or the per-packet PAD/CRC ENABLE is set,
CRC ENABLE is ignored. This bit is cleared by default.
0 Frames presented to the MAC have a valid length and contain a valid CRC.
1 The MAC appends a CRC on all frames. Clear this bit if frames presented to the MAC have a valid
Full duplex configure. This bit is cleared by default.
0 The MAC operates in half-duplex mode only.
1 The MAC operates in full-duplex mode.
(MAXFRM[Maximum Frame]) and limit the length of frames transmitted to less than the maximum
frame length.
See
received frames. See
information.
Transmitted frames are not checked.
Magic Packet.
MACCFG1. In this mode the MAC ignores all received frames until the specific Magic Packet frame
is received, at which point this bit is cleared by the eTSEC, and a maskable interrupt through
IEVENT[MAG] occurs.
padding requirement.
length and contain a valid CRC.
Receive or transmit > maximum frame length
Receive
Transmit
Receive or transmit < maximum frame length
Table 14-44. MACCFG2 Field Descriptions (continued)
Section 14.6.8, “Buffer
Frame type
Section 14.5.3.5.5, “Maximum Frame Length Register
= maximum frame length
= maximum frame length
Descriptors,” for further details of buffer descriptor bit updating.
Frame length
Description
Enhanced Three-Speed Ethernet Controllers
truncation
Packet
yes
no
no
no
Buffer descriptor
(MAXFRM),” for further
updated
yes
yes
no
no
14-77