MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 878

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 14-123
14.5.3.11.9 Timer Accumulator Register (TMR_ACC)
Timer accumulator register accumulates the value of the addend register into it. An overflow pulse of the
accumulator is used to increment the timer clock by TMR_CTRL[TCLK_PERIOD]. This register is read
only in normal operation. The register in eTSEC1 is shared for all eTSECs. Figure 14-116 describes the
definition of the TMR_ACC register.
Table 14-124
14.5.3.11.10 Timer Prescale Register (TMR_PRSC)
Timer generated output clock prescale register. It is used to adjust output clock frequency that is put onto
the 1588 clock output signal. The register in eTSEC1 is shared for all eTSECs. Figure 14-117 describes
the definition for the TMR_PRSC register.
14-130
0–31
0–31
Bits
Bits
Offset eTSEC1:0x2_4E24
Offset eTSEC1:0x2_4E28
Reset
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
W
W
R
R
TMR_ACC
ADDEND
0
0
Name
Name
describes the fields of the TMR_ADD register fields for the timer.
describes the fields of the TMR_ACC register.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
For example,
TimerOsc = 50 MHz
NominalFreq = 40 MHz
FreqDivRatio = 1.25
ADDEND = ceil(2^32/1.25) = 0xCCCC_CCCD
Timer drift compensation addend register value. It is programmed with a value of 2^32/FreqDivRatio.
32-bit timer accumulator register
Table 14-123. TMR_ADD Register Field Descriptions
Table 14-124. TMR_ACC Register Field Descriptions
Figure 14-117. TMR_PRSC Register Definition
Figure 14-116. TMR_ACC Register Definition
—
TMR_ACC
All zeros
15 16
Description
Description
PRSC_OCK
Access: Read/Write
Access: Read/Write
Freescale Semiconductor
31
31