MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 687

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.4.1.3
The three memory controllers in the eLBC generate an internal transfer acknowledge signal, TA, to allow
data on LAD to be either sampled (for reads) or changed (on writes). The data sampling/data change
always occurs at the end of the bus cycle in which the eLBC asserts TA internally. In eLBC debug mode,
TA is also visible externally on the MDVAL pin. The GPCM controller automatically generates TA
according to the timing parameters programmed for them in the option and mode registers; FCM generates
TA whenever data read and write instructions are executed out of register FIR; a UPM generates TA only
when a UPM pattern has the UTA RAM word bit set.
Note that TA and LALE are never asserted together, and that for the duration of LALE, LCSn (or any other
control signal) remains negated or frozen.
Freescale Semiconductor
LA[27:31]
LCLK
LALE
LCS n
LWE
LAD[0:7]
LAD[8:31]
LDP[0]
LDP[1:3]
Figure 13-30. Example of 8-Bit GPCM Writing 32 Bytes to Address 0x5420 (LCRR[PBYP] = 0)
Data Transfer Acknowledge (TA)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Note: All address and signal values are shown in hexadecimal.
00
54
20
0
0
00
D(B
P(B
D(Bk) = k
0
0
)
)
00
54
21
0
0
th
of 32 data bytes, P(Bk) = parity bit of k
01
D(B
P(B
1
1
)
)
00
54
22
0
0
02
D(B
P(B
2
2
)
)
Figure 13-31
03
00
54
23
0
0
1C
54
3D
shows LALE, TA (internal), and LCSn.
00
0
0
th
data byte.
1D
D(B
P(B
29
29
)
)
54
3E
00
0
0
Enhanced Local Bus Controller
1E
D(B
P(B
30
30
)
)
00
54
3F
0
0
1F
D(B
P(B
31
31
)
)
13-45