MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 881

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The three registers in eTSEC1 are shared for all eTSECs. Figure 14-120 describes the definition for the
TMR_FIPER register.
Table 14-128
14.5.3.11.14 External Trigger Stamp Register (TMR_ETTS1–2_H/L)
General purpose external trigger -stamp register (TMR_ETTSn_H/L). This register holds time at the
programmable edge of the external trigger. The registers in eTSEC1 are shared for all eTSECs. This
register is read only in normal operation. Figure 14-121 describes the definition for the TMR_ETTSn_H/L
register.
Table 14-129
14.5.4
This section describes the ten-bit interface (TBI), reduced ten-bit interface (RTBI), and the TBI/RTBI MII
set of registers. TBI and RTBI operate in the same manner (the only difference is that RTBI has reduced
I/O signalling).
Freescale Semiconductor
Offset eTSEC1:0x2_4EA0+8 n
Reset
Offset eTSEC1:0x2_4E80+4* n
Reset 1
0–31
0–63
Bits
Bits
W
W
R
R
0
0
1
ETTS_H/L Time stamp field at the programmable edge of the external trigger.
FIPER
Ten-Bit Interface (TBI)
Name
Name
1
describes the fields of the TMR_FIPER register.
describes the fields of the TMR_ETTSn_H/L register.
1
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Fixed interval pulse period register. This field must be programmed to an integer multiple of
TMR_CTRL[TCLK_PERIOD] value to ensure a period pulse being generated correctly.
1
Table 14-129. TMR_ETTS1-2_H Register Field Descriptions
1
Table 14-128. TMR_FIPER Register Field Descriptions
ETTS_H
Figure 14-121. TMR_ETTS1-2_H/L Register Definition
1
Figure 14-120. TMR_FIPER n Register Definition
1
1
1
1
1
1
1
All zeros
31 32
FIPER
1
1
Description
Description
1
1
1
1
Enhanced Three-Speed Ethernet Controllers
1
1
ETTS_L
1
1
1
1
Access: Read/Write
Access: Read/Write
1
1
1
14-133
1
31
1
63