MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 718

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
Figure 13-62
cycle type. RUN commands (MxMR[OP] = 11), however, can initiate patterns starting at any of the 64
UPM RAM words.
13.4.4.1.1
The user must ensure that the UPM is appropriately initialized before a request occurs.
The UPM supports two types of memory reads and writes:
The user must ensure that patterns for single-beat transfers contain one, and only one, transfer
acknowledge (UTA bit in RAM word set high) and for a burst transfer, contain the exact number of transfer
acknowledges required.
13-76
•
•
A single-beat transfer transfers one operand consisting of up to a single word (dependent on port
size). A single-beat cycle starts with one transfer start and ends with one transfer acknowledge.
A burst transfer transfers exactly 4 double words regardless of port size. For 32-bit accesses, the
burst cycle starts with one transfer start but ends after eight transfer acknowledges, whereas an
8-bit device requires 32 transfer acknowledges.
Exception Condition Request
and
Memory Access Requests
Read Single-Beat Request
Write Single-Beat Request
Table 13-39
Refresh Timer Request
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Read Burst Request
Write Burst Request
Read single-beat (RSS)
Read burst (RBS)
Write single-beat (WSS)
Write burst (WBS)
Refresh timer (RTS)
Exception condition (EXS)
show the start addresses of these patterns in the UPM RAM, according to
Table 13-39. UPM Routines Start Addresses
UPM Routine
Figure 13-62. RAM Array Indexing
Array Index
Generator
WSS
WBS
RSS
RBS
EXS
RTS
Routine Start Address
0x3C
0x00
0x08
0x18
0x20
0x30
RAM Array
Freescale Semiconductor
64 RAM
Words